CS8130-CS Cirrus Logic Inc, CS8130-CS Datasheet - Page 12
![IC IR TRANSCEIVER 2-5V 20-SSOP](/photos/6/84/68424/cs8130-cs_sml.jpg)
CS8130-CS
Manufacturer Part Number
CS8130-CS
Description
IC IR TRANSCEIVER 2-5V 20-SSOP
Manufacturer
Cirrus Logic Inc
Type
Transceiverr
Datasheet
1.CS8130-CS.pdf
(28 pages)
Specifications of CS8130-CS
Mounting Type
Surface Mount
Voltage - Supply
2.7 V ~ 5.5 V
Package / Case
20-SSOP
Logic Case Style
SSOP
No. Of Pins
20
Peak Reflow Compatible (260 C)
No
Supply Voltage Max
5.5V
Transceiver Type
Infrared
Driver Case Style
SSOP
Leaded Process Compatible
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
598-1161 - BOARD EVAL FOR CS8130
Number Of Drivers/receivers
-
Protocol
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
Other names
598-1203-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS8130-CSZ
Manufacturer:
CIRRUS
Quantity:
20 000
Reset
Bringing the RESET pin low will force the inter-
nal logic, including the control registers, into a
known state, provided the PWRDN pin is high.
RESET is disabled if the PWRDN pin is low.
The reset state is given in each register definition
table. RESET must be low for >25 ms if using
the crystal oscillator (see Clock Generation
above).
Control Register Definitions
The various control registers within the CS8130
may be written by setting the D/C pin to low,
and sending characters from the UART to the
TXD pin. The characters are interpreted as a 4-
bit address field and a 4-bit data field, as shown
in Figure 7. After the control character is re-
ceived and written into the control register, it is
optionally echoed back out the RXD pin. The
baud rate used for this control mode is whatever
is currently set in the baud rate register. If the
"load baud rate" bit is written to, then the new
baud rate takes effect after the character has been
echoed back, if echo is enabled. Otherwise, the
new baud rate is effective immediately.
One of the control registers contains a shadow
register set enable bit, which effectively becomes
the MSB of the 5-bit register address. Hence
there are 31 4-bit registers. The shadow bit must
be written to a 1 to allow access to the registers
with addresses 16 through 31. The shadow bit
RXD
12
12
TXD
D/C
Start
Bit
CD0
CD1
Data
CD2
CD3
AD0
AD1
Address
Figure 7. Control Mode Timing
AD2
AD3
Stop
Bit
register is always accessible, independent of the
state of the shadow bit. The shadow bit must be
written to 0 to enable access to registers 0
through 15.
The following tables define the detailed function
of all the registers inside the CS8130.
Start
Bit
CD0
CD1
Data
CD2
CD3
AD0
AD1
Address
AD2
CS8130
CS8130
AD3
DS134PP2
DS134F1
Stop
Bit