ST7538QTR STMicroelectronics, ST7538QTR Datasheet
ST7538QTR
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ST7538QTR Summary of contents
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... UART/SPI host interface ■ ST7537 compatible Order codes Part number ST7538Q ST7538QTR July 2006 FSK power line transceiver TQFP44 Slug Down Description The ST7538Q is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and two linear regulators for 5V and 3 ...
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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST7538Q 6 Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 Band in use . . . ...
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Block diagram 1 Block diagram Figure 1. Block diagram AVdd AVss CARRIER CD/PD DETECTION RxD CLR/T PLL UART/SPI SERIAL INTERFACE REG/DATA RxTx TxD REGOK OSC TIME BASE XOut XIn WD TOUT 4/44 TEST1 TEST2 TEST DIGITAL FSK IF FILTER DEMOD ...
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ST7538Q 2 Pin settings 2.1 Pin connection Figure 2. Pin Connection (Top view CD_PD 1 DVSS 2 RXD 3 RxTx 4 TXD 5 GND 6 TOUT 7 CLR DVDD ...
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Pin settings 2.2 Pin description Table 1. Pin description Pin N° Name Type 1 CD_PD Digital/Output 2 DVss Supply 3 RxD Digital/Output 4 RxTx Digital/Input with internal pull-up 5 TxD Digital/Input with internal pull-down 6 GND Supply 7 TOUT Digital/Output ...
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ST7538Q Table 1. Pin description (continued) Pin N° Name Type 25 SGND Supply 26 XOUT Analog Output 27 XIN Analog Input 28 AVdd Supply 29 (3) Analog/Input Vsense 30 TEST2 Analog/Input 31 RxFO Analog/Output 32 RAI Analog/Input 33 VDC Power ...
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Electrical data 3 Electrical data 3.1 Maximum ratings Table 2. Absolute maximum ratings Symbol PAV Power Supply Voltage CC AV Analog Supply Voltage dd DV Digital Supply Voltage dd AV /DV Voltage between Digital input Voltage ...
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ST7538Q 3.2 Thermal data Table 3. Thermal data Symbol Maximum Thermal Resistance Junction-Ambient R thJA1 Steady state Maximum Thermal Resistance Junction-Ambient R thJA2 Steady state 1. Mounted on Multilayer PCB with a dissipating surface on the bottom side of the ...
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Electrical characteristics Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ T other control register parameters as default value, unless otherwise specified) Symbol Parameter Digital I/O 5V digital ...
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ST7538Q Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ T other control register parameters as default value, unless otherwise specified) Symbol Parameter Second Harmonic HD2 ATO Distortion ...
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Electrical characteristics Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ T other control register parameters as default value, unless otherwise specified) Symbol Parameter Input capacitance on CL ...
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ST7538Q Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ T other control register parameters as default value, unless otherwise specified) Symbol Parameter 5V voltage regulator Linear regulator ...
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Electrical characteristics Table 4. Electrical characteristics (continued) (AVdd = DVdd = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V, -40°C ≤ T other control register parameters as default value, unless otherwise specified) Symbol Parameter Baud rate Bit Time ...
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ST7538Q 5 Functional description 5.1 Carrier frequencies ST7538Q is a multi frequency device: eight programmable Carrier Frequencies are available (see Table 5). Only one Carrier could be used a time. The communication channel could be varied during the normal working ...
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Functional description 5.3 Mark and space frequencies Mark and space communication frequencies are defined by the following formula: F ("0") = FCarrier + [ F ("1") = FCarrier - [ ∆F is the Frequency Deviation. With Deviation = “0.5” the ...
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ST7538Q Table 7. ST7538Q synthesized frequencies Carrier Baud Frequency Rate (KHz) 72 600 1200 2400 4800 76 600 1200 2400 4800 5.4 ST7538Q mains access ST7538Q can access the Mains in two different ways: ● Synchronous access ● Asynchronous access ...
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Functional description In Data Reception Mode: – Synchronous Mains access: on clock signal recovered by a PLL from ST7538Q (CLR/T line) rising edge, value on FSK Demodulator is read and put to the data reception line (RxD line). ST7538Q recovers ...
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ST7538Q The UART interface allows to connect an UART compatible device instead SPI interface allows to connect an SPI compatible device. The allowed combinations of Host Interface/ST7538Q Mains Access are: Table 9. Host Interface / ST7538Q mains access combinations Host ...
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Functional description 5.5.1 Communication between host and ST7538Q The Host can achieve the Mains access by selecting REG_DATA = ”0” and the choice between Data Transmission or Data Reception is performed by selecting RxTx line (if RxTx =“1” ST7538Q receives ...
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ST7538Q Figure 5. Data reception -> data transmission -> data reception CLR_T T B RxD REG_DATA RxTx TxD 5.6 Control register access The communication with ST7538Q Control Register is always synchronous. The access is achieved using the same lines of ...
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Functional description Figure 6. Data reception -> control register read -> data reception timing diagram CLR_T RXD REG_DATA RxTx Figure 7. Data reception -> control register write -> data reception timing diagram CLR_T ...
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ST7538Q 5.7 Receiving mode The receive section is active when RxTx Pin = ”1” and REG_DATA = 0. The input signal is read on RAI Pin using SGND as ground reference and then pre-filtered by a Band pass Filter (62kHz ...
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Functional description Figure 10. ST7538Q PLL lock-in range CLR/T RxD 5.7.3 Carrier/preamble detection The Carrier/Preamble Block is a digital Frequency detector Circuit. It can be used to manage the MAINS access and to detect an incoming signal. Two are the ...
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ST7538Q Figure 11. CD_PD timing during RX CD_PD RAI RxD (UART/SPI="1") RxD (UART/SPI="0") Figure 12. Receiving path block diagram 3 RxD Bits 3-4 &14 8 CLR/T PLL Bits 18-21 & 24-47 HEADER 1 CD_PD RECOGN DCD ...
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Functional description 5.8 Transmission mode The transmit mode is set when RxTx Pin = ”0” and REG_DATA Pin = ”0”. In transmitting mode the FSK Modulator and the Power Line Interface are turned ON. The transmit Data (TXD) enter synchronously ...
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ST7538Q 5.8.1 Automatic Level Control (ALC) The Automatic Level Control Block (ALC variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB ...
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Functional description Voltage control loop formula Table 10. Vout vs R1 & R2 resistors value Vout (Vrms) 0.150 0.250 0.350 0.500 0.625 0.750 0.875 1.000 1.250 1.500 Note: The rate of R2 takes in account the input resistance on the ...
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ST7538Q ● Integrated Power Line Interface (PLI) The Power Line Interface (PLI double CMOS AB Class Power Amplifier with the two outputs (ATOP1 and ATOP2) in opposition of phase. Two are the possible configuration: - Single Ended Output ...
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Functional description Figure 17. PLI startup timing diagram RX/TX ATOP2 5.9 Crystal oscillator ST7538Q integrates a inverter driver circuit to realize a 16MHz crystal oscillator. This circuit is able to drive a maximum load capacitance of 16pF with typical quartz ...
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ST7538Q Figure 19. XIN waveform if an external oscillator is used 5.10 Control register The ST7538Q is a multi-channel and multifunction transceiver. An internal Bits (in Extended mode) Control Register allows to manage all the programmable parameters ...
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Functional description Table 11. Control register functions Bits Function Frequencies Baud Rate 5 Deviation 6 Watchdog Transmission Time Out Frequency detection time Zero Crossing 11 Synchronizati on 32/44 ...
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ST7538Q Table 11. Control register functions (continued) Function Detection Method Mains 14 Interfacing Mode 15 to Output Clock 16 Output 17 Voltage Level Freeze Header 18 Recognition Frame 19 Length Count Value Selection Bit 13 Carrier detection ...
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Functional description Table 11. Control register functions (continued) Function Header 20 Length Extended 21 Register Sensitivity 22 Mode 23 Input Filter 24 to Frame 39 Header 40 to Frame 47 Length 1. The Detection method bit meaning differs depending on ...
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ST7538Q 5.11 Detection method and Rx Sensitivity in UART mode When ST7538Q is running in UART mode (by forcing UART/SPI pin to “1”) the Control Register Function “Detection method” differs from SPI mode as indicated in the Table 12. Control ...
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Auxiliary analog and digital functions 6 Auxiliary analog and digital functions 6.1 Band in use The Band in Use Block has a Carrier Detection like function but with a different Input Sensibility (77dBµV Typ.) and with a different BandPass filter ...
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ST7538Q Figure 21. Reset and watchdog timing T RSTO RSTO WD 6.4 Zero crossing detection The Mains Voltage Zero Crossing can be detected, through a proper connection of ZCIN to the Mains. ZCIN comparator has a threshold fixed at SGND. ...
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Auxiliary analog and digital functions 6.5 Output clock MCLK is the master clock output. The clock frequency sourced can be programed through the control register ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4) or can be ...
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ST7538Q 6.11 5V and 3.3V voltage regulators and power good function ST7538Q has an embedded 5V linear regulator externally available to supply the application circuitry. The linear regulator has a very low quiescent current (50µA) and a current capability of ...
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Auxiliary analog and digital functions 6.12 Power-up procedure To ensure ST7538Q proper power-Up sequence, PAVcc, AVdd and DVdd Supply has to fulfil the following rules: PAVcc rising slope must not exceed 100V/ms. When DVdd is below 5V/3.3V and AVdd is ...
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ST7538Q Figure 25. Application schematic example with coupling tranformer. Auxiliary analog and digital functions 41/44 ...
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Package mechanical data 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package ...
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ST7538Q 8 Revision history Table 13. Revision history Date 12-Jul-2006 Revision 1 Initial release. Revision history Changes 43/44 ...
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