PIC16F877-20/P Microchip Technology Inc., PIC16F877-20/P Datasheet - Page 22
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PIC16F877-20/P
Manufacturer Part Number
PIC16F877-20/P
Description
40 PIN, 7 KB FLASH, 368 RAM, 33 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F877-20P.pdf
(218 pages)
Specifications of PIC16F877-20/P
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
33
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Serial Interface
MSSP, USART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F87X
2.2.2.3
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3:
DS30292C-page 20
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON Register
INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
- n = Value at POR
R/W-0
GIE
the bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared
(must be cleared in software).
R/W-0
PEIE
R/W-0
T0IE
W = Writable bit
’1’ = Bit is set
R/W-0
INTE
Note:
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
RBIE
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0
T0IF
2001 Microchip Technology Inc.
x = Bit is unknown
R/W-0
INTF
R/W-x
RBIF
bit 0