DP83848KSQ/NOPB National Semiconductor, DP83848KSQ/NOPB Datasheet - Page 61

IC TXRX ETHERNET PHYTER 40-LLP

DP83848KSQ/NOPB

Manufacturer Part Number
DP83848KSQ/NOPB
Description
IC TXRX ETHERNET PHYTER 40-LLP
Manufacturer
National Semiconductor
Type
Transceiverr
Datasheet

Specifications of DP83848KSQ/NOPB

Number Of Drivers/receivers
1/1
Protocol
Ethernet
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
40-LLP
For Use With
DP83848K-MAU-EK - BOARD EVALUATION DP83848K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DP83848KSQ
DP83848KSQTR

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8.2 AC SPECS
8.2.1 Power Up Timing
Note: In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84 ms.
T2.1.1
T2.1.2
T2.1.3
Dual Function Pins
Become Enabled As Outputs
Parameter
Latch-In of Hardware
Configuration Pins
RESET_N
Hardware
X1 clock
Post Power Up Stabilization
time prior to MDC preamble for
register accesses
Hardware Configuration Latch-
in Time from power up
Hardware Configuration pins
transition to output drivers
MDC
Vcc
Description
MDIO is pulled high for 32-bit serial man-
agement initialization
X1 Clock must be stable for a min. of
167ms at power up.
Hardware Configuration Pins are de-
scribed in the Pin Description section
X1 Clock must be stable for a min. of
167ms at power up.
T2.1.2
T2.1.1
61
Notes
input
T2.1.3
output
Min
167
167
32 clocks
Typ
50
www.national.com
Max
Units
ms
ms
ns

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