DS90CR287MTD/NOPB National Semiconductor, DS90CR287MTD/NOPB Datasheet - Page 5

• Manufacturer Part Number: DS90CR287MTD/NOPB
• Description: IC TX 28BIT CHAN LINK 56TSSOP
• Manufacturer: National Semiconductor
• Type: Driverr

Specifications of DS90CR287MTD/NOPB

• Number Of Drivers/receivers: 3/0
• Protocol: RS644
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Supply Current: 60mA
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: TSSOP
• No. Of Pins: 56
• Operating Temperature Range: -10°C To +70°C
• Msl: MSL 2 - 1 Year
• Device Type: Line
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Esd Hbm: 7kV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS90CR287MTD; *DS90CR287MTD/NOPB; DS90CR287MTD

CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Symbol
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference
(both dependent on type/length of cable), and source clock (less than 150 ps).
Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
AC Timing Diagrams
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
Receiver Input Strobe Position for Bit 0 (Figure 15)
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure 16)
RxCLK OUT Period (Figure 6)
RxCLK OUT High Time (Figure 6)
RxCLK OUT Low Time (Figure 6)
RxOUT Setup to RxCLK OUT (Figure 6)
RxOUT Hold to RxCLK OUT (Figure 6)
RxCLK IN to RxCLK OUT Delay
Receiver Phase Lock Loop Set (Figure 10)
Receiver Powerdown Delay (Figure 13)
FIGURE 1. “Worst Case” Test Pattern
@
Parameter
25˚C, V
CC
= 3.3V (Note 6)(Figure 8)
5
f = 85 MHz
f = 85 MHz
f = 85 MHz
10.57
11.76
0.49
2.17
3.85
5.53
7.21
8.89
Min
290
3.5
3.5
3.5
5.5
4
10.92
0.84
2.52
4.20
5.88
7.56
9.24
Typ
1.8
2
T
5
5
7
10108702
11.27
Max
1.19
2.87
4.55
6.23
7.91
9.59
3.5
3.5
6.5
9.5
50
10
6
1
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Units
ms
ns
ns
ns
ns
ns
ns
ns
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ps
ns
ns
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µs