GAL20RA10B-20LP Lattice, GAL20RA10B-20LP Datasheet
GAL20RA10B-20LP
Specifications of GAL20RA10B-20LP
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GAL20RA10B-20LP Summary of contents
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... GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... GAL20RA10 Ordering Information Commercial Grade Specifications Industrial Grade Specifications Part Number Description GAL20RA10B Device Name Speed (ns Low Power Power Specifications GAL20RA10 XXXXXXXX Grade Blank = Commercial I = Industrial Package P = Plastic DIP J = PLCC ...
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Output Logic Macrocell (OLMC) The GAL20RA10 OLMC consists flip-flops with indi- vidual asynchronous programmable reset, preset and clock product terms. The sum of four product terms and an Exclusive-OR pro- vide a programmable polarity D-input to each ...
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... The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T Specifications GAL20RA10B Recommended Operating Conditions (1) Commercial Devices: +1 ...
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... Preload Hold Time 1) Refer to Switching Test Conditions section. 2) Refer to fmax Descriptions section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL20RA10B Over Recommended Operating Conditions COM COM -7 -10 MIN. MAX. MIN. MAX ...
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Descriptions CLK LOGIC REGISTER ARRAY max with External Feedback 1/( Note: fmax with external feedback is cal- culated from measured tsu and tco. Switching Test Conditions Input Pulse Levels Input Rise and -7/-10 Fall Times ...