PIC16F818-I/SO Microchip Technology Inc., PIC16F818-I/SO Datasheet - Page 16

• Manufacturer Part Number: PIC16F818-I/SO
• Description: 18 PIN, 1.75 KB FLASH, 128 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F818-I/SO

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F818/819
TABLE 2-1:
DS39598E-page 14
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1:
Bank 1
(1)
(1)
(1)
(1)
(1)
(1,2)
(1)
2:
3:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PIE2
PCON
OSCCON
OSCTUNE
PR2
SSPADD
SSPSTAT
ADRESL
ADCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register Low Byte
TRISA7
RBPU
ADFM
Bit 7
SMP
GIE
IRP
—
—
—
—
—
—
INTEDG
TRISA6
ADCS2
IRCF2
ADIE
Bit 6
PEIE
CKE
RP1
—
—
—
—
TRISA5
TMR0IE
IRCF1
T0CS
TUN5
Bit 5
RP0
D/A
2
—
—
—
—
—
C™ mode) Address Register
(3)
PORTA Data Direction Register (TRISA<4:0>
Write Buffer for the upper 5 bits of the PC
IRCF0
TUN4
T0SE
INTE
Bit 4
EEIE
TO
—
—
—
P
PCFG3
SSPIE
TUN3
RBIE
Bit 3
PSA
PD
—
—
—
S
TMR0IF
CCP1IE
PCFG2
TUN2
IOFS
Bit 2
R/W
PS2
—
—
Z
TMR2IE
PCFG1
TUN1
Bit 1
INTF
POR
PS1
DC
UA
—
—
 2004 Microchip Technology Inc.
TMR1IE
PCFG0
TUN0
RBIF
Bit 0
BOR
PS0
BF
—
—
C
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
---0 0000
0000 000x
-0-- 0000
---0 ----
---- --qq
-000 -0--
--00 0000
1111 1111
0000 0000
0000 0000
xxxx xxxx
00-- 0000
POR, BOR
Value on
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Details on
17, 54
71, 76
page:
23
23
16
23
39
43
23
18
19
21
22
38
36
68
72
81
82
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