DS21348G+ Maxim Integrated Products, DS21348G+ Datasheet - Page 19

• Manufacturer Part Number: DS21348G+
• Description: IC LIU T1/E1/J1 3.3V 49-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS21348G+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 49-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MM0/MM1
RT0/RT1
RRING
SCLKE
NAME
MCLK
RNEG
RCLK
NRZE
PBEO
TCLK
RPOS
RTIP/
RCL
NA
18/19
44/23
27/28
PIN
24
40
25
39
38
30
—
43
3
4
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional. G.703 requires an accuracy of ±50ppm for
both T1 and E1. TR62411 and ANSI specs require an accuracy of
±32ppm for T1 interfaces.
Monitor Mode Select Bits 0 and 1 [H/W Mode]. These inputs
determine if the receive equalizer is in a monitor mode
Not Assigned. Should be tied low.
NRZ Enable [H/W Mode]
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
PRBS Bit Error Output. The receiver will constantly search for a
QRSS (T1) or a 2
mode is selected. Remains high if out of synchronization with the
PRBS pattern. Goes low when synchronized to the PRBS pattern.
Any errors in the received pattern after synchronization will cause a
positive going pulse (with same period as E1 or T1 clock)
synchronous with RCLK.
Receive Clock. Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
Receive Carrier Loss. An output which will toggle high during a
receive carrier loss.
Receive Negative Data. Updated on the rising edge (CES = 0) or
the falling edge (CES = 1) of RCLK with the bipolar data out of the
line interface. Set NRZE to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
Section
Receive Positive Data. Updated on the rising edge (CES = 0) or the
falling edge (CES = 1) of RCLK with bipolar data out of the line
interface. Set NRZE pin to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
section
Receive LIU Termination Select Bits 0 and 1 [H/W Mode]. These
inputs determine the receive termination. See
Receive Tip and Ring. Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section
for details.
Receive and Transmit Synchronization Clock Enable
0 = disable 2.048MHz synchronization transmit and receive mode
1 = enable 2.048 Hz synchronization transmit and receive mode
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to
clock data through the transmit side formatter.
6.4
6.4
for details.
for details.
19 of 76
15
-1 (E1) PRBS depending whether T1 or E1
FUNCTION
Table
2-12.
(Table
2-11).
5