DS2154L+ Maxim Integrated Products, DS2154L+ Datasheet - Page 58

• Manufacturer Part Number: DS2154L+
• Description: IC TXRX E1 1CHIP 5V ENH 100-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2154L+

• Number Of Drivers/receivers: 1/1
• Protocol: E1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 1.544 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current (max): 75 mA (Typ)
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 100
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS2154
12 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS2154 provides for access to both the Sa and the Si bits via three different methods. The first is via
a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is discussed in
Section 12.1. The second involves using the internal RAF/RNAF and TAF/TNAF registers and is
discussed in Section 12.2. The third method, which is covered in Section 12.3, involves an expanded
version of the second method and is one of the features added to the DS2154 from the original DS2153
definition.
12.1 Hardware Scheme
On the receive side, all the received data is reported at the RLINK pin. Via RCR2, the user can control
the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can
be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will
identify the Si bits. See Section
14
for detailed timing.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see
Section
12.2
for details) or from the external TLINK pin. Via TCR2, the DS2154 can be programmed to
source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits
through the DS2154 without them being altered, then the device should be set up to source all five Sa bits
via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through the
TSER pin via the clearing of the TCR1.3 bit. See the timing diagrams and the transmit data flow diagram
in Section
14
for examples.
12.2 Internal Register Scheme Based on Double-Frame
On the receive side, the RAF and RNAF registers will always report the data as it received in the
Additional and International bit locations. The RAF and RNAF registers are updated with the setting of
the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to
read the RAF and RNAF registers. It has 250µs to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250µs to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if either the DS2154 is programmed: (1) to source the Si bits
from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa
bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1 (see Section
12.1
for
details). See the register descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram
(Figure
14-11) for more details.
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