DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 34

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.
11.1 PRBS Generator and Detector
Each LIU has built-in pseudorandom bit sequence (PRBS) generator and detector circuitry for physical layer
testing. The device generates and detects unframed 2
O.151 specification. To transmit a PRBS pattern, pull the TDSA and TDSB pins high (hardware mode) or set
configuration bits TDSA and TDSB in the
generator automatically generates 2
The PRBS detector, which is always enabled
and CPU bus modes) or through the PRBS and PBER status bits (CPU bus mode). When the PRBS detector is out
of synchronization, the PRBS pin is forced high. When the detector syncs to an incoming PRBS pattern, the PRBS
pin is driven low, then pulses high, synchronous with RCLK, for each bit error detected. See
11-2
and set to zero when the detector syncs to an incoming PRBS pattern. A change of state of the PRBS bit sets the
PRBSL bit in the
is set to one. A pattern bit error set the PBERL bit in the
PBERIE bit in the
Figure 11-1. PRBS Output with Normal RCLK Operation
Figure 11-2. PRBS Output with Inverted RCLK Operation
11.2 Loopbacks
Each LIU has three internal loopbacks. See
LLB and RLB control bits in the
loopbacks are disabled. Setting RLB = 1 with LLB = 0 enables remote loopback, which loops recovered clock and
data back through the LIU transmitter. During remote loopback, recovered clock and data are output on RCLK,
RPOS/RDAT, and RNEG/RLCV, but the TPOS/TDAT and TNEG pins are ignored. Setting LLB = 1 with RLB = 0
enables analog local loopback, which loops the outgoing transmit signal back to the receiver’s analog front end.
Setting LLB = RLB = 1 enables digital local loopback, which loops digital transmit clock and data back to the
receiver’s digital circuitry, including the LOS detector, the B3ZS/HDB3 decoder, and the PRBS detector. When
either of the local loopbacks is enabled, the transmit signal is output normally on TXP/TXN, but the received signal
on RXP/RXN is ignored.
for details. In CPU bus mode, the PRBS status bit is set to one when the detector is out of synchronization
PRBS
RCLK
PRBS
RCLK
DIAGNOSTICS
PRBS DETECTOR
PRBS DETECTOR
IS NOT IN SYNC
IS NOT IN SYNC
SRL
SRIE
register and can also cause an interrupt on the INT pin if the PRBSIE bit in the
register is set to one.
PRBS PIN PULSES HIGH FOR EACH BIT
PRBS PIN PULSES HIGH FOR EACH BIT
RCINV = 1
RCINV = 0
PRBS DETECTOR IS IN SYNC; THE
PRBS DETECTOR IS IN SYNC; THE
GCR
ERROR DETECTED
15
ERROR DETECTED
- 1 for DS3 and STS-1 modes and 2
register (CPU bus mode) enable these loopbacks. When LLB = RLB = 0,
Figure 4-1
(Table
GCR
register (CPU bus mode). As
6-H), reports its status through the PRBS output pin (hardware
34 of 71
15
and
- 1 (DS3 or STS-1) or 2
Figure
SRL
4-2. The LLB and RLB pins (hardware mode) or
register and can also cause an interrupt if the
23
- 1 for E3 mode.
23
- 1 PRBS, according to the ITU
Table 6-G
Figure 11-1
shows, the PRBS
SRIE
and
register
Figure