PIC16F628-20/P Microchip Technology Inc., PIC16F628-20/P Datasheet - Page 104

• Manufacturer Part Number: PIC16F628-20/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628-20/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: SCI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F62X
DS40300C-page 102
14.6.1
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The RB0/INT
interrupt can wake-up the processor from SLEEP, if the
INTE bit was set prior to going into SLEEP. The status
of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 14.9 for details on SLEEP, and Figure 14-17
for timing of wake-up from SLEEP through RB0/INT
interrupt.
FIGURE 14-15:
Note 1: INTF flag is sampled here (every Q1).
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
PC
Instruction
Fetched
Instruction
Executed
INSTRUCTION FLOW
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
3: CLKOUT is available in ER and INTRC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
on
(3)
RB0/INT INTERRUPT
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
the
Q1
Inst (PC-1)
RB0/INT
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
(4)
Q3
pin,
(5)
Q4
Q1
the
Inst (PC+1)
Inst (PC)
(1)
Q2
INTF
PC+1
Q3
Preliminary
bit
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
14.6.2
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
14.6.3
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RBIE (INTCON<4>)
bit. For operation of PORTB (Section 5.2).
14.6.4
See Section 9.6 for complete description of comparator
interrupts.
PC+1
—
Note:
Q3
enabled/disabled
Q4
(2)
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
TMR0 INTERRUPT
PORTB INTERRUPT
COMPARATOR INTERRUPT
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
 2003 Microchip Technology Inc.
Q3
by
Q4
setting/clearing
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
T0IE