DS3150QN+ Maxim Integrated Products, DS3150QN+ Datasheet - Page 17

• Manufacturer Part Number: DS3150QN+
• Description: IC LIU T3/E3/STS-1 28-PLCC
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3150QN+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 28-LCC, 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. PIN DESCRIPTIONS
Pins are listed in alphabetical order. Section
Table 2-A. Pin Descriptions
NAME
MCLK
LBKS
LBO
LOS
EFE
DM
ICE
(Note 2)
(Note 2)
(Note 2)
TYPE
I3
I3
I3
I3
O
O
I
Active-Low Driver Monitor (Open Drain). When the transmit driver monitor detects
a faulty transmitter, DM is driven low. Requires an external pullup to V
out in the PLCC package.
Enhanced Feature Enable. EFE enables the enhanced DS3150 features (PRBS
generation/detection and the transmission of patterns, including all ones, DS3 AIS, and
the 1010… pattern).
0 = enhanced features disabled: TDS0 and TDS1 ignored and PRBS tri-stated
1 = enhanced features enabled: TDS0, TDS1, and PRBS active
loat = test mode enabled: TDS0, TDS1, LBO, LOS redefined as test pins
Invert Clock Enable. ICE determines on which RCLK edge RPOS/RNRZ and
RNEG/RLCV are updated and on which TCLK edge TPOS/TNRZ and TNEG are
sampled.
0 = Normal RCLK/Normal TCLK: update RPOS/RNRZ and RNEG/RLCV on falling
edge of RCLK; sample TPOS/TNRZ and TNEG on rising edge of TCLK
1 = Normal RCLK/Inverted TCLK: update RPOS/RNRZ and RNEG/RLCV on falling
edge of RCLK; sample TPOS/TNRZ and TNEG on falling edge of TCLK
Float = Inverted RCLK/Inverted TCLK: update RPOS/RNRZ and RNEG/RLCV on
rising edge of RCLK; sample TPOS/TNRZ and TNEG on falling edge of TCLK
Active-Low Loopback Select. LBKS determines if either the analog loopback or the
remote loopback is enabled. See the block diagram in
0 = analog loopback enabled
1 = no loopback enabled
Float = remote loopback enabled
Line Build-Out. LBO indicates cable length for waveform shaping in DS3 and STS-1
modes. LBO is ignored for E3 mode and should be wired high or low.
0 = cable length ³ 225ft
1 = cable length < 225ft
Active-Low Loss of Signal. LOS is asserted upon detection of 175 ±75 consecutive
zeros in the receive data stream. LOS is deasserted when there are no excessive zero
occurrences over a span of 175 ±75 clock periods. An excessive zero occurrence is
defined as three or more consecutive zeros in the DS3 and STS-1 modes or four or more
zeros in the E3 mode. See Section
Master Clock. If the signal on MCLK is toggling, the device assumes it is a
transmission-quality clock (44.736MHz for DS3, 34.368MHz for E3, 51.840MHz for
STS-1, ±20ppm, low jitter) and uses it as its master clock. The duty cycle of the applied
clock signal should be between 30% and 70%. If MCLK is wired high or left floating,
the device uses the signal on the TCLK pin as the master clock. If MCLK is wired low,
the device takes its master clock from an internal oscillator. The frequency of this
oscillator is determined by a resistor placed between the OFSEL pin and V
has an internal 15kW pullup resistor to V
and CDR blocks.
4
shows the pin configurations for both packages.
17 of 28
1.2
FUNCTION
for additional details.
DD
. The selected master clock is used by the JA
Figure 1-1
for details.
DD
. Not bonded
SS
. MCLK