FIN1531M Fairchild Semiconductor, FIN1531M Datasheet - Page 3

IC DRIVER QUAD 5V HS LVDS 16SOIC

FIN1531M

Manufacturer Part Number
FIN1531M
Description
IC DRIVER QUAD 5V HS LVDS 16SOIC
Manufacturer
Fairchild Semiconductor
Type
Driverr
Datasheet

Specifications of FIN1531M

Number Of Drivers/receivers
4/0
Protocol
LVDS
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Logic Family
FIN15
Logic Type
High Speed Differential Driver
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Data Rate
400 Mbps
Interface
EIA/TIA-644
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
/ /
Supply Current
26 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
FIN1531M_NL
FIN1531M_NL

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t
t
t
t
t
t
t
t
f
t
t
t
t
PLHD
PHLD
TLHD
THLD
SK(P)
SK(LH)
SK(HL)
SK(PP)
MAX
ZHD
ZLD
HZD
LZD
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3: All typical values are at T
Note 4: t
tion.
Note 5: t
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: f
Note 7: Test Circuits in Figure 2 and Figure 4 are simplified representations of test fixture and DUT loading.
Symbol
,
SK(LH)
SK(PP)
MAX
Differential Propagation Delay
LOW-to-HIGH
Differential Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%) See Figure 2 and Figure 3 (Note 7)
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency(Note 6)
LVTTL Output Enable Time from Z to HIGH R
LVTTL Output Enable Time from Z to LOW See Figure 4 and Figure 5 (Note 7)
LVTTL Output Disable Time from HIGH to Z
LVTTL Output Disable Time from LOW to Z
Criteria: Input t
, t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
PLH
R
Parameter
t
- t
F
A
PHL
1 ns, 0V to 3V, 50% Duty Cycle; Output V
25 C and with V
|
CC
5V.
R
L
L
100 , C
100 , C
Test Conditions
L
L
OD
3
10 pF,
10 pF,
250 mV, 45% to 55% Duty Cycle; all output channels switching in phase.
Min
200
0.5
0.5
0.6
0.6
(Note 3)
Typ
250
1.4
1.4
0.8
0.8
www.fairchildsemi.com
Max
2.0
2.0
1.2
1.2
0.4
0.3
1.0
5.0
5.0
5.0
5.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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