PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 265

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

25.6.5
A Repeated Start condition occurs when the RSEN bit
of the SSPxCON2 register is programmed high and the
Master state machine is no longer active. When the
RSEN bit is set, the SCLx pin is asserted low. When the
SCLx pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDAx pin is released
(brought high) for one Baud Rate Generator count
(T
SDAx is sampled high, the SCLx pin will be deasserted
(brought high). When SCLx is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDAx
and SCLx must be sampled high for one T
action is then followed by assertion of the SDAx pin
(SDAx = 0) for one T
asserted low. Following this, the RSEN bit of the
FIGURE 25-27:
 2011 Microchip Technology Inc.
BRG
). When the Baud Rate Generator times out, if
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
BRG
REPEAT START CONDITION WAVEFORM
SDAx
SCLx
while SCLx is high. SCLx is
Write to SSPxCON2
occurs here
SDAx = 1,
SCLx (no change)
BRG
. This
T
BRG
SDAx = 1,
SCLx = 1
T
BRG
Repeated Start
SSPxCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDAx pin held low. As soon as a Start condition is
detected on the SDAx and SCLx pins, the S bit of the
SSPxSTAT register will be set. The SSPxIF bit will not
be set until the Baud Rate Generator has timed out.
Sr
Note 1: If RSEN is programmed while any other
T
BRG
PIC16(L)F1826/27
2: A bus collision during the Repeated Start
S bit set by hardware
At completion of Start bit,
hardware clears RSEN bit
Write to SSPxBUF occurs here
event is in progress, it will not take effect.
condition occurs if:
and sets SSPxIF
• SDAx is sampled low when SCLx
• SCLx goes low before SDAx is
T
BRG
goes from low-to-high.
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
1st bit
T
BRG
DS41391D-page 265