MCP3201-BI/P Microchip Technology Inc., MCP3201-BI/P Datasheet - Page 15

• Manufacturer Part Number: MCP3201-BI/P
• Description: A/D Converter, 12-Bit, 2.7V, SPI, Single Channel, PDIP-8
• Manufacturer: Microchip Technology Inc.

Specifications of MCP3201-BI/P

• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

6.0
6.1
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3201. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3201 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3201 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3201. Figure 6-1 depicts the operation shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the A/D Converter
on the falling edge of the third clock pulse. After the first
eight clocks have been sent to the device, the micro-
FIGURE 6-1:
FIGURE 6-2:
© 2007 Microchip Technology Inc.
D
CLK
D
CS
CLK
OUT
CS
OUT
APPLICATIONS INFORMATION
Using the MCP3201 with
Microcontroller SPI Ports
HI-Z
HI-Z
Data stored into MCU receive register
after transmission of first 8 bits
?
Data stored into MCU receive register
after transmission of first 8 bits
1
?
1
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
?
2
?
2
NULL
BIT
NULL
0
BIT
3
0
3
B11 B10
B11 B10 B9
B11 B10 B9
B11 B10
4
4
5
5
B9
6
B9
6
B8
B8
7
B8
B8
7
B7
B7
8
B7
B7
8
B6
Data stored into MCU receive register
after transmission of second 8 bits
B6 B5
B6
9
B6
Data stored into MCU receive register
after transmission of second 8 bits
9
B5
10
B5
B5
10
B4
B4
11
B4
B4
11
B3
B3
12
B3
controller’s receive buffer will contain two unknown bits
(the output is at high impedance for the first two
clocks), the null bit and the highest order five bits of the
conversion. After the second eight clocks have been
sent to the device, the MCU receive register will contain
the lowest order seven bits and the B1 bit repeated as
the A/D Converter has begun to shift out LSB first data
with the extra clock. Typical procedure would then call
for the lower order byte of data to be shifted right by one
bit to remove the extra B1 bit. The B7 bit is then trans-
ferred from the high order byte to the lower order byte,
and then the higher order byte is shifted one bit to the
right as well. Easier manipulation of the converted data
can be obtained by using this method.
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
B3
12
B2
B2
13
B2 B1
B2
13
B1
B1
14
B1
14
B0
B0
15
B0
B0
15
B1
B1
16
B1
16
B1
B2
HI-Z
HI-Z
LSB first data begins
to come out
Data is clocked out of A/D
Converter on falling edges
MCU latches data from A/D
Converter on rising edges of SCLK
MCU latches data from A/D
Converter on rising edges of SCLK
Data is clocked out of A/D
Converter on falling edges
LSB first data begins
to come out
MCP3201
DS21290D-page 15