PIC16F870-I/SP Microchip Technology Inc., PIC16F870-I/SP Datasheet - Page 168

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PIC16F870-I/SP

Manufacturer Part Number
PIC16F870-I/SP
Description
28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F870-I/SP

A/d Inputs
5-Channel, 10-Bit
Cpu Speed
5 MIPS
Eeprom Memory
64 Bytes
Input Output
22
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F870-I/SP
Manufacturer:
MICROCHIP
Quantity:
5 600
Part Number:
PIC16F870-I/SP
Quantity:
2 871
PIC16F870/871
U
Universal Synchronous Asynchronous Receiver Transmitter.
USART ................................................................................ 61
DS30569B-page 166
See USART
Address Detect Enable (ADDEN Bit) .......................... 62
Asynchronous Mode ................................................... 66
Asynchronous Receive ............................................... 68
Asynchronous Receive (9-bit Mode) ........................... 70
Asynchronous Receive with Address Detect.
Asynchronous Reception ............................................ 69
Asynchronous Transmitter .......................................... 66
Baud Rate Generator (BRG)....................................... 63
Clock Source Select (CSRC Bit) ................................. 61
Continuous Receive Enable (CREN Bit) ..................... 62
Framing Error (FERR Bit) ........................................... 62
Overrun Error (OERR Bit) ........................................... 62
Receive Data, 9th bit (RX9D Bit) ................................ 62
Receive Enable, 9-bit (RX9 Bit) .................................. 62
Serial Port Enable (SPEN Bit)............................... 61, 62
Single Receive Enable (SREN Bit) ............................. 62
Synchronous Master Mode ......................................... 72
Synchronous Master Reception .................................. 74
Synchronous Master Transmission............................. 72
Synchronous Slave Mode ........................................... 76
Synchronous Slave Reception .................................... 77
Synchronous Slave Transmit ...................................... 76
Transmit Data, 9th Bit (TX9D)..................................... 61
Transmit Enable (TXEN Bit)........................................ 61
Transmit Enable, Nine-bit (TX9 Bit) ............................ 61
Transmit Shift Register Status (TRMT Bit).................. 61
See Asynchronous Receive (9-bit Mode).
Baud Rate Formula............................................. 63
Baud Rates, Asynchronous Mode
Baud Rates, Asynchronous Mode
High Baud Rate Select (BRGH Bit)..................... 61
Sampling ............................................................. 63
(BRGH = 0) ................................................. 64
(BRGH = 1) ................................................. 65
W
Wake-up from SLEEP................................................. 87, 100
Watchdog Timer
Watchdog Timer (WDT)................................................ 87, 99
Write Verify
WWW, On-Line Support ....................................................... 4
Interrupts .................................................................... 93
MCLR Reset ............................................................... 93
Timing Diagram ........................................................ 101
WDT Reset ................................................................. 93
Register Summary ...................................................... 99
Enable (WDTEN Bit)................................................... 99
Postscaler. See Postscaler, WDT.
Programming Considerations ..................................... 99
RC Oscillator............................................................... 99
Time-out Period .......................................................... 99
WDT Reset, Normal Operation............................. 91, 93
WDT Reset, SLEEP.............................................. 91, 93
Data EEPROM and FLASH Program Memory ........... 31
 2003 Microchip Technology Inc.

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