PIC16F716-I/SS Microchip Technology Inc., PIC16F716-I/SS Datasheet - Page 17

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PIC16F716-I/SS

Manufacturer Part Number
PIC16F716-I/SS
Description
MCU, 8-Bit, 2KW Flash, 128 RAM, 13 I/O, SSOP-20
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F716-I/SS

A/d Inputs
4-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
13
Memory Type
Flash
Number Of Bits
8
Package Type
20-pin SSOP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F716-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.2.2.5
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 2-5:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-3
bit 2
bit 1
bit 0
U-0
PIR1 Register
Unimplemented: Read as ‘0’
ADIF: A/D Interrupt Flag bit
1 = A/D conversion complete
0 = A/D conversion has not completed or has not been started
Unimplemented: Read as ‘0’
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match has not occurred
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Timer1 register overflowed (must be cleared in software)
0 = Timer1 has not overflowed
R/W-0
ADIF
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
CCP1IF
U-0
software
x = Bit is unknown
PIC16F716
TMR2IF
R/W-0
should
DS41206B-page 15
ensure
TMR1IF
R/W-0
bit 0
the

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