24LC1025-I/P Microchip Technology Inc., 24LC1025-I/P Datasheet - Page 5

• Manufacturer Part Number: 24LC1025-I/P
• Description: 1024K, 128K X 8, 2.5V SER EE, 128 BYTE PAGE, PDIP-8
• Manufacturer: Microchip Technology Inc.

Specifications of 24LC1025-I/P

• Capacitance, Input: 10 pF
• Capacitance, Output: 10 pF
• Current, Input, Leakage: ±1 μA
• Current, Operating: 450 μA (Read), 5 mA (Write)
• Density: 1024K
• Interface: 2-Wire
• Memory Type: Serial EEPROM
• Organization: 1024K×8
• Package Type: PDIP
• Temperature, Operating: -40 to +85 °C
• Time, Access: 900 ns
• Time, Fall: 300 ns
• Time, Rise: 300 ns
• Voltage, Esd: ≥4 kV
• Voltage, Input, High: 1.75 V
• Voltage, Input, Low: 0.75 V
• Voltage, Output, Low: 0.4 V
• Voltage, Supply: 2.5 to 5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
The A0 and A1 inputs are used by the 24XX1025 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2
The A2 input is non-configurable Chip Select. This pin
must be tied to V
2.3
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
© 2008 Microchip Technology Inc.
Name PDIP SOIJ
SDA
SCL
V
V
WP
A0
A1
A2
SS
CC
PIN DESCRIPTIONS
A0, A1 Chip Address Inputs
A2 Chip Address Input
Serial Data (SDA)
1
2
3
4
5
6
7
8
CC
CC
1
2
3
4
5
6
7
8
PIN FUNCTION TABLE
(typical 10 kΩ for 100 kHz, 2 kΩ for
in order for this device to operate.
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard-wired to
logical 1 state (V
will not operate with this pin
left floating or held to logical 0
(V
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA1025)
+2.5 to 5.5V (24LC1025)
+1.8 to 5.5V (24FC1025)
SS
).
Function
24AA1025/24LC1025/24FC1025
CC
). Device
2.4
This input is used to synchronize the data transfer from
and to the device.
2.5
This pin must be connected to either V
to V
write operations are inhibited, but read operations are
not affected.
SS
, write operations are enabled. If tied to V
Serial Clock (SCL)
Write-Protect (WP)
DS21941F-page 5
SS
or V
CC
. If tied
CC
,