PIC17C756A-33/L Microchip Technology Inc., PIC17C756A-33/L Datasheet - Page 151
PIC17C756A-33/L
Manufacturer Part Number
PIC17C756A-33/L
Description
68 PIN, 32 KB OTP, 902 RAM, 50 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC17C756A-33L.pdf
(304 pages)
Specifications of PIC17C756A-33/L
A/d Inputs
12-Channel, 10-Bit
Cpu Speed
8.25 MIPS
Eeprom Memory
0 Bytes
Input Output
52
Interface
I2C/SPI/USART
Memory Type
OTP
Number Of Bits
8
Package Type
68-pin PLCC
Programmable Memory
32K Bytes
Ram Size
902 Bytes
Speed
16 MHz
Timers
2-8-bit, 2-16-bit
Voltage, Range
3-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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15.2.5
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
FIGURE 15-17:
2000 Microchip Technology Inc.
SDA
SCL
MASTER MODE
SSP BLOCK DIAGRAM (I
2
C bus may be taken when the
SDA In
Bus Collision
SCL In
Read
Write Collision Detect
MSb
START bit, STOP bit,
START bit Detect,
end of XMIT/RCV
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
SSPBUF
Generate
SSPSR
2
C MASTER MODE)
LSb
Write
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
Clock
Data Bus
Shift
Internal
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
PIC17C7XX
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
DS30289B-page 151
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