PIC16F628-04I/P Microchip Technology Inc., PIC16F628-04I/P Datasheet - Page 85

• Manufacturer Part Number: PIC16F628-04I/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628-04I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: SCI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.4.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RB1/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
RESET by the hardware. In this case, it is RESET
when the RCREG register has been read and is empty.
The RCREG is a double buffered register (i.e., it is a
two-deep FIFO). It is possible for two bytes of data to
be received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
 2003 Microchip Technology Inc.
Address
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
by
PIR1
RCSTA
RCREG USART Receive Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
USART SYNCHRONOUS MASTER
RECEPTION
Name
setting
EEPIE
CSRC
SPEN
Bit 7
EEIF
either
CMIF
CMIE
Bit 6
RX9
TX9
enable
SREN CREN
TXEN SYNC
RCIF
RCIE
Bit 5
bit
Bit 4
TXIF
TXIE
SREN
Preliminary
ADEN
Bit 3
—
—
—
CCP1IE TMR2IE TMR1IE -000 0000
CCP1IF TMR2IF TMR1IF 0000 -000
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
BRGH
FERR
Bit 2
Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1)
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
OERR
TRMT
Bit 1
RX9D
TX9D
Bit 0
PIC16F62X
0000 -00x
0000 0000
0000 -010
0000 0000
Value on:
POR
DS40300C-page 83
Value on all
0000 -000
0000 -00x
0000 0000
-000 -000
0000 -010
0000 0000
RESETS
other