PIC16F818-I/P Microchip Technology Inc., PIC16F818-I/P Datasheet - Page 39

• Manufacturer Part Number: PIC16F818-I/P
• Description: 18 PIN, 1.75 KB FLASH, 128 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F818-I/P

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.5.3
The OSCCON register (Register 4-2) controls several
aspects of the system clock’s operation.
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source (31.25 kHz), the INTOSC source
(8 MHz) or one of the six frequencies derived from the
INTOSC postscaler (125 kHz to 4 MHz). Changing the
configuration of these bits has an immediate change on
the multiplexor’s frequency output.
4.5.4
The IRCF bits can be modified at any time regardless of
which clock source is currently being used as the
system clock. The internal oscillator allows users to
change the frequency during run time. This is achieved
by modifying the IRCF bits in the OSCCON register.
The sequence of events that occur after the IRCF bits
are modified is dependent upon the initial value of the
IRCF bits before they are modified. If the INTRC
(31.25 kHz, IRCF<2:0> = 000) is running and the IRCF
bits are modified to any other value than ‘000’, a 4 ms
(approx.) clock switch delay is turned on. Code execu-
tion continues at a higher than expected frequency
while the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit in the OSCCON register to
become set before continuing. This bit can be
monitored to ensure that the frequency is stable before
using the system clock in time critical applications.
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz, IRCF<2:0>
4 ms (approx.) clock switch delay. The new INTOSC
frequency will be stable immediately after the eight
falling edges. The IOFS bit will remain set after clock
switching occurs.
 2004 Microchip Technology Inc.
Note:
OSCILLATOR CONTROL REGISTER
MODIFYING THE IRCF BITS
Caution must be taken when modifying the
IRCF bits using BCF or BSF instructions. It
is possible to modify the IRCF bits to a
frequency that may be out of the V
ification range; for example, V
and IRCF = 111 (8 MHz).
000), there is no need for a
DD
DD
= 2.0V
spec-
4.5.5
Following are three different sequences for switching
the internal RC oscillator frequency.
• Clock before switch: 31.25 kHz (IRCF<2:0> = 000)
• Clock before switch: One of INTOSC/INTOSC
• Clock before switch: One of INTOSC/INTOSC
1. IRCF bits are modified to an INTOSC/INTOSC
2. The clock switching circuitry waits for a falling
3. The clock switching circuitry then waits for eight
4. The IOFS bit is clear to indicate that the clock is
5. Switchover is complete.
postscaler (IRCF<2:0>
1. IRCF
2. The clock switching circuitry waits for a falling
3. The clock switching circuitry then waits for eight
4. Oscillator switchover is complete.
postscaler (IRCF<2:0>
1. IRCF bits are modified to a different INTOSC/
2. The clock switching circuitry waits for a falling
3. The clock switching circuitry then waits for eight
4. The IOFS bit is set.
5. Oscillator switchover is complete.
postscaler frequency.
edge of the current clock, at which point CLKO
is held low.
falling edges of requested clock, after which it
switches CLKO to this new clock source.
unstable and a 4 ms (approx.) delay is started.
Time dependent code should wait for IOFS to
become set.
(IRCF<2:0> = 000).
edge of the current clock, at which point CLKO
is held low.
falling edges of requested clock, after which it
switches CLKO to this new clock source.
INTOSC postscaler frequency.
edge of the current clock, at which point CLKO
is held low.
falling edges of requested clock, after which it
switches CLKO to this new clock source.
CLOCK TRANSITION SEQUENCE
WHEN THE IRCF BITS ARE
MODIFIED
bits
PIC16F818/819
are
modified
000)
000)
DS39598E-page 37
to
INTRC