PIC16F916-I/SO Microchip Technology Inc., PIC16F916-I/SO Datasheet - Page 143
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16F916-I/SO
Manufacturer Part Number
PIC16F916-I/SO
Description
28 PIN, 14 KB FLASH, 352 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F916-ISO.pdf
(272 pages)
Specifications of PIC16F916-I/SO
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
14K Bytes
Ram Size
352 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F916-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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FIGURE 11-11:
11.4
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK/SCK/SCL/SEG9 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in Sleep mode.
Slave mode is entered by clearing bit, CSRC
(TXSTA<7>).
11.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
© 2005 Microchip Technology Inc.
SDI/SDA/SEG8
RC6/TX/CK/
SCK/SCL/SEG9
RC7/RX/DT/
(Interrupt)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
CREN bit
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
bit SREN
SREN bit
RCIF bit
RXREG
Write to
Read
USART Synchronous Slave Mode
Q2
USART SYNCHRONOUS SLAVE
TRANSMIT
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
‘0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4
bit 1
bit 2
Preliminary
PIC16F917/916/914/913
bit 3
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
bit 4
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
bit 5
bit 6
bit 7
DS41250E-page 141
Q1Q2Q3Q4
‘0’
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