MCP6292-E/SN Microchip Technology Inc., MCP6292-E/SN Datasheet - Page 4
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
MCP6292-E/SN
Manufacturer Part Number
MCP6292-E/SN
Description
DUAL 10 MHZ OP, E TEMP
Manufacturer
Microchip Technology Inc.
Datasheet
1.MCP6292-ESN.pdf
(6 pages)
Specifications of MCP6292-E/SN
Amplifier Type
General Purpose, Power, Rail-to-Rail, Single Supply
Bandwidth
10 MHz
Common Mode Rejection Ratio
85
Current, Input Bias
2 nA
Current, Input Offset
±1 pA
Current, Output
±30 mA
Current, Supply
±30 mA
Number Of Amplifiers
Dual
Package Type
SOIC-8
Slew Rate
7
Temperature, Operating, Range
-40 to +125 °C
Voltage, Gain
110 dB
Voltage, Input
2.1 to 2.7 V
Voltage, Noise
8.7 nV/sqrt Hz
Voltage, Offset
+3 mV
Voltage, Output, High
2385 mV
Voltage, Output, Low
2385 mV
Voltage, Supply
2.4 to 6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP6292-E/SN
Manufacturer:
Nuvoton
Quantity:
107
Part Number:
MCP6292-E/SN
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
MCP6291/1R/2/3/4/5
TEMPERATURE SPECIFICATIONS
FIGURE 1-1:
Chip Select (CS) pin on the MCP6293 and
MCP6295.
DS21812E-page 4
Electrical Characteristics: Unless otherwise indicated, V
Temperature Ranges
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 6L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
CS
V
I
I
SS
CS
Note:
OUT
-0.7 µA
(typical)
0.7 µA
(typical)
Hi-Z
The Junction Temperature (T
Parameters
V
t
IL
ON
Timing Diagram for the
-1.0 mA
(typical)
10 nA
(typical)
J
) must not exceed the Absolute Maximum specification of +150°C.
V
0.7 µA
(typical)
IH
t
-0.7 µA
(typical)
OFF
Sym
θ
θ
θ
θ
θ
θ
θ
θ
T
T
Hi-Z
JA
JA
JA
JA
JA
JA
JA
JA
A
A
DD
= +2.4V to +5.5V and V
Min
-40
-65
—
—
—
—
—
—
—
—
1.1
The test circuits used for the DC and AC tests are
shown in
capacitors are laid out according to the rules discussed
in Section 4.6 “Supply Bypass”.
FIGURE 1-2:
Most Non-Inverting Gain Conditions.
FIGURE 1-3:
Most Inverting Gain Conditions.
V
V
V
V
DD
DD
Typ
256
230
163
206
120
100
85
70
—
—
IN
IN
/2
/2
Test Circuits
R
R
R
R
N
G
N
G
Figure 1-2
SS
+125
+150
Max
—
—
—
—
—
—
—
—
= GND.
MCP629X
MCP629X
V
V
AC and DC Test Circuit for
AC and DC Test Circuit for
DD
DD
Units
and
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
© 2007 Microchip Technology Inc.
°C
°C
0.1 µF
0.1 µF
R
R
Figure
F
F
Note
1 µF
1 µF
1-2. The bypass
Conditions
C
C
L
L
V
V
L
L
V
R
V
R
OUT
OUT
L
L