PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 137

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

DECFSZ
Syntax:
Operands:
Operation:
Status Affected: None
Description:
GOTO
Syntax:
Operands:
Operation:
Status Affected: None
Description:
INCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
© 2005 Microchip Technology Inc.
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0
d
(f) – 1
skip if result = 0
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register ‘f’.
If the result is ‘1’, the next instruction
is executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
Unconditional Branch
[ label ]
0
k
PCLATH<4:3>
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two-cycle
instruction.
Increment f
[ label ]
0
d
(f) + 1
Z
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
f
k
[0,1]
PC<10:0>
f
[0,1]
127
2047
127
(destination);
GOTO k
(destination)
INCF f,d
PC<12:11>
PIC12F635/PIC16F636/639
Preliminary
INCFSZ
Syntax:
Operands:
Operation:
Status Affected: None
Description:
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Increment f, Skip if 0
[ label ]
0
d
(f) + 1
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the
result is placed back in
register ‘f’.
If the result is ‘1’, the next instruction
is executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
skip if result = 0
Inclusive OR W with f
[ label ]
0
d
(W) .OR. (f)
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Inclusive OR Literal with W
[ label ]
0
(W) .OR. k
Z
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
f
[0,1]
f
[0,1]
k
127
127
255
(destination),
INCFSZ f,d
IORWF
IORLW k
(W)
(destination)
DS41232B-page 135
f,d