PIC16F883-I/ML Microchip Technology Inc., PIC16F883-I/ML Datasheet - Page 209
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16F883-I/ML
Manufacturer Part Number
PIC16F883-I/ML
Description
28 PIN, 7KB FLASH, 256 RAM, 25 I/O, QFN
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F883-IML.pdf
(328 pages)
Specifications of PIC16F883-I/ML
A/d Inputs
11-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Frequency
20 MHz
Input Output
24
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
7K Bytes
Ram Size
256 Bytes
Resistance, Drain To Source On
Bytes
Serial Interface
MSSP or EUSART
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F883-I/ML
Manufacturer:
MICROCHIP
Quantity:
1 200
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13.4.16.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 13-26:
FIGURE 13-27:
© 2008 Microchip Technology Inc.
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is
sampled low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
SDA
PEN
SCL
Bus Collision During a Stop
Condition
P
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
Assert SDA
T
SDA asserted low
BRG
T
BRG
PIC16F882/883/884/886/887
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 13-26). If the SCL pin is sam-
pled low before SDA is allowed to float high, a bus col-
lision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 13-27).
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
‘
‘
0
0
DS41291E-page 207
’
’
SDA sampled
low after T
set BCLIF
‘
‘
0
0
’
’
BRG
,
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