PIC18F26K80-E/SS Microchip Technology Inc., PIC18F26K80-E/SS Datasheet - Page 470
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC18F26K80-E/SS
Manufacturer Part Number
PIC18F26K80-E/SS
Description
28 SSOP .209IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F26K80-E/SS
A/d Inputs
8-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SSOP
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
- Current page: 470 of 628
- Download datasheet (6Mb)
PIC18F66K80 FAMILY
REGISTER 28-8:
DS39977C-page 470
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-0
Note 1:
R/C-1
CPD
For the memory size of the blocks, see
CPD: Data EEPROM Code Protection bit
1 = Data EEPROM is not code-protected
0 = Data EEPROM is code-protected
CPB: Boot Block Code Protection bit
1 = Boot block is not code-protected
0 = Boot block is code-protected
Unimplemented: Read as ‘ 0 ’
R/C-1
CPB
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
(1)
U-0
Preliminary
—
Figure
(1)
28-6. The boot block size changes with BBSIZ0.
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
U-0
—
2011 Microchip Technology Inc.
x = Bit is unknown
U-0
—
U-0
—
bit 0
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