DS1245Y-70+ Dallas Semiconductor, DS1245Y-70+ Datasheet - Page 6

• Manufacturer Part Number: DS1245Y-70+
• Description: SRAM, Nonvolatile, 128k x 8, 70 nS, DIP32
• Manufacturer: Dallas Semiconductor

Specifications of DS1245Y-70+

• Capacitance, Input: 5 pF
• Capacitance, Output: 5 pF
• Current, Input, Leakage: ±1 μA
• Current, Operating: 85 mA
• Current, Output, Leakage: ±1
• Data Retention: 10 yrs.
• Density: 1024K
• Interface: Parallel Bus
• Memory Type: Non-Volatile SRAM
• Organization: 128K×8
• Package Type: 740 EMOD
• Temperature, Operating: 0 to +70 °C
• Time, Access: 70 ns
• Time, Address Hold: 5
• Time, Fall: 5 ns
• Time, Rise: 5 ns
• Voltage, Input, High: 5 V
• Voltage, Input, Low: 0.8 V
• Voltage, Supply: 5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

POWER-DOWN/POWER-UP TIMING
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
2.
3. t
4. t
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
7. If the
8. If
9. Each DS1245 has a built-in switch that disconnects the lithium source until the user first applies V
10. Each DS1245 has a built-in switch that disconnects the lithium source until V
11. All AC and DC electrical characteristics are valid over the full operating temperature range. For
12. In a power-down condition the voltage on any pin may not exceed the voltage on V
PARAMETER
V
V
V
V
V
PARAMETER
Expected Data Retention Time
CC
CC
CC
CC
CC
going low to the earlier of
buffers remain in a high impedance state during this period.
buffers remain in high impedance state during this period.
the output buffers remain in a high impedance state during this period.
The expected t
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production testing.
user. The expected t
power is first applied by the user.
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
OE
WE
WP
DH
Fail Detect to
slew from V
slew from 0V to V
Valid to
Valid to End of Write Protection
WE
, t
= V
is specified as the logical AND of
is high for a Read Cycle.
DS
CE
CE
is low or the
are measured from the earlier of
IH
or V
low transition occurs simultaneously with or latter than the
high transition occurs prior to or simultaneously with the
CE
TP
IL
and
DR
. If
CE
to 0V
is defined as accumulative time in the absence of V
WE
and
OE
TP
DR
WE
Inactive
is defined as accumulative time in the absence of V
= V
WE
low transition occurs prior to or simultaneously with the
CE
IH
Inactive
during write cycle, the output buffers remain in a high impedance state.
or
WE
going high.
SYMBOL
SYMBOL
CE
CE
t
t
t
t
REC
or
and
t
t
DR
PD
PU
R
F
WE
8 of 13
WE
going high.
. t
MIN
MIN
150
150
WP
10
is measured from the latter of
TYP
TYP
CC
WE
WE
MAX
MAX
starting from the time power
125
1.5
2
high transition, the output
low transition, the output
CC
CC
(t
starting from the time
is first applied by the
A
UNITS
UNITS
: See Note 10)
CC
CE
years
ms
ms
μs
μs
μs
.
low transition,
(t
DS1245Y/AB
CE
A
NOTES
=25°C)
NOTES
or
11
9
WE
CC
.