V386G IDT, Integrated Device Technology Inc, V386G Datasheet

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V386G

Manufacturer Part Number
V386G
Description
IC RCVR 8BIT LVDS VID 56-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Receiverr
Datasheet

Specifications of V386G

Protocol
LVDS
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Drivers/receivers
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
V386GLFT
Manufacturer:
SHARP
Quantity:
65
V386 Datasheet
I DT • 2 0 6 4 S i l v e r C r e ek Va l l e y R o a d, S a n J os e , CA 9 5 1 3 8 • t e l ( 8 0 0 ) 3 4 5 - 7 0 1 5 • w w w. i dt . c o m
General Description
The V386 is an ideal LVDS receiver that converts 4-pair
LVDS data streams into parallel 28 bits of CMOS/TTL
data with bandwidth up to 2.38 Gbps throughput or
297.5 Mbytes per second.
This chip is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL
interfaces through very low-swing LVDS signals.
Pin Assignments
LVDS_GND
LVDS_GND
LVDS_GND
LVDS_VCC
RxCLKOUT
RxCLKIN+
PWRDWN
PLL_GND
PLL_GND
RxOUT22
RxOUT23
RxOUT24
RxOUT25
RxOUT26
RxOUT27
RxCLKIN-
PLL_VCC
RxOUT0
RxIN0+
RxIN1+
RxIN2+
RxIN3+
RxIN0-
RxIN1-
RxIN2-
RxIN3-
GND
GND
V386
8-B
IT
10
11
12
13
14
15
16
17
18
19
25
26
27
28
1
2
3
4
5
6
7
8
9
20
21
22
23
24
56-pin TSSOP
LVDS R
V386
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
ECEIVER FOR
VCC
RxOUT21
RxOUT20
RxOUT19
GND
RxOUT18
RxOUT17
RxOUT16
VCC
RxOUT15
RxOUT14
RxOUT13
GND
RxOUT12
RxOUT11
RxOUT10
VCC
RxOUT9
RxOUT8
RxOUT7
GND
RxOUT6
RxOUT5
RxOUT4
RxOUT3
VCC
RxOUT2
RxOUT1
1
RxCLKIN+
PWRDWN
RxCLKIN-
RxIN0+
RxIN1+
RxIN2+
RxIN3+
RxIN0-
RxIN1-
RxIN2-
RxIN3-
Features
Block Diagram
Converts 4-pair LVDS data streams into parallel 28
bits of CMOS/TTL data
Fully spread spectrum compatible
Wide clock frequency range from 15 MHz to 85 MHz
Supports VGA, SVGA, XGA, and SXGA
LVDS voltage swing of 350 mV for low EMI
On-chip PLL requires no external components
Low-power CMOS design
Falling edge clock triggered outputs
Power-down control function
Compatible with TIA/EIA-644 LVDS standards
Packaged in a 56-pin TSSOP (Pb free available)
Pin and function compatible with the National
DS90CF386, THine THC63LVDF84, TI
SN65LVDS94
V
IDEO
V386
LVDS to TTL
De-serializer
PLL
7/5/07
8
8
8
RED
GREEN
BLUE
HSYNC
DATA ENABLE
CONTROL
VSYNC
RxCLKOUT
Revision 2.2

Related parts for V386G

V386G Summary of contents

Page 1

V386 8-B LVDS R IT General Description The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second. This ...

Page 2

V386 8-B LVDS R IT ECEIVER FOR Pin Descriptions Pin Pin name Type 1 RxOUT22 OUT 2 RxOUT23 OUT 3 RxOUT24 OUT 4 GND Ground 5 RxOUT25 OUT 6 RxOUT26 OUT 7 RxOUT27 OUT 8 LVDS_GND Ground 9 RxIN0- LVDS ...

Page 3

V386 8-B LVDS R IT ECEIVER FOR Pin Pin name Type 34 RxOUT5 OUT 35 RxOUT6 OUT 36 GND Ground 37 RxOUT7 OUT 38 RxOUT8 OUT 39 RxOUT9 OUT 40 VCC Power 41 RxOUT10 OUT 42 RxOUT11 OUT 43 RxOUT12 ...

Page 4

V386 8-B LVDS R IT ECEIVER FOR Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the V386. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation ...

Page 5

V386 8-B LVDS R IT ECEIVER FOR Parameter Output Short Circuit Current LVDS Receiver DC Specifications Differential Input High Threshold Differential Input Low Threshold Input Current Receiver Supply Current Receiver Supply Current (worst case) Receiver Supply Current (16 Grayscale) Receiver ...

Page 6

V386 8-B LVDS R IT ECEIVER FOR Parameter Receiver Input Strobe Position for Bit5 Receiver Input Strobe Position for Bit6 RxIn Skew Margin (see note and Figure 8) Note: The skew margins mean the maximum timing tolerance between the clock ...

Page 7

V386 8-B LVDS R IT ECEIVER FOR Timing Diagrams CLKIN/CLKOUT ODD Data In/Data Out EVEN Data In/Data Out Figure 1a. “Worst Case” Test Pattern CLKOUT D0 D1 D2, 10, 18 D3, 11, 19 D4-7, 12-15, 20-23 ...

Page 8

V386 8-B LVDS R IT ECEIVER FOR 0.8 V CLKOUT D0 – D27 Out Figure 3. V386 SETUP/HOLD and High/Low Times RCK CLKOUT Figure 4. V386 Clock In to Clock Out Delay 2.0 V PWRDWN 3.0 V VCC RCK CLKOUT ...

Page 9

V386 8-B LVDS R IT ECEIVER FOR Clock Previous Cycle Data Rspos0 Min Rspos0 Max Rspos1 Min Rspos1 Max Rspos2 Min Rspos2 Max Figure 7. V386 LVDS Input Strobe Position RCK+/RCK- RX[n]+/RX[n Figure 8. ...

Page 10

... V386GLF V386GLF V386GLFT V386GLF Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

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