ST802RT1BFR STMicroelectronics, ST802RT1BFR Datasheet - Page 44

• Manufacturer Part Number: ST802RT1BFR
• Description: TXRX ETH 10/100 REAL TIME 48LQFP
• Manufacturer: STMicroelectronics
• Type: Transceiverr

Specifications of ST802RT1BFR

• Number Of Drivers/receivers: 1/1
• Protocol: Ethernet
• Voltage - Supply: 3.15 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Operating Supply Voltage: 3.3 V
• Supply Current: 4.5 mA
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Power Dissipation Pd: 315 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10431

Device operation
7.15
Figure 7.
7.16
7.17
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Transmit isolation
Transmit isolation
Transmit isolation isolates the PHY from the MII and Tx +/- interface and is activated by
setting bit 5 of the 100Base-TX control register (RN13[5]). As with isolate mode, all MII
inputs are ignored and all MII outputs are tri-stated. Additionally, all link pulses are
suppressed.
Automatic MDI / MDIX feature
The automatic MDI / MDIX feature compensates for using an external crossover cable. With
auto-MDIX, the ST802RT1x automatically detects what the other device is and switches the
TX & RX pins accordingly. The state machine basically controls the switching of the tdp/tdn
and the rdp/rdn signals prior to the auto-negotiation communication. The swapping occurs
to allow FLP/NLP to be transmitted and received in the event that the external cable
connections have been swapped.
RMII interface
The reduced media independent interface (RMII) provides a low-cost alternative to the IEEE
802.3u MII interface. It can support 10 and 100 Mbit data rates with a single clock, using
independent 2-bit wide transmit and receive paths. A single synchronous reference clock
(SCLK pin 32) of 50 MHz is used as a timing reference for all transmitters and receivers. By
doubling the clock frequency relative to the MII, four pins are saved in the data path, which
uses two transmit data inputs and two receive data outputs instead of four lines for each
direction in the MII interface. Since start-of-packet and end-of-packet timing information is
preserved across the interface, the MAC is able to derive the COL signal from the receive
and transmit data delimiters, saving another pin.
Doc ID 17049 Rev 1
ST802RT1A, ST802RT1B