IDT82P2288BB IDT, Integrated Device Technology Inc, IDT82P2288BB Datasheet - Page 291

• Manufacturer Part Number: IDT82P2288BB
• Description: TXRX T1/J1/E1 8CHAN 256-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Transceiverr

Specifications of IDT82P2288BB

• Protocol: IEEE 1149.1
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2288BB

E1 FGEN Maintenance 1 (06CH, 16CH, 26CH, 36CH, 46CH, 56CH, 66CH, 76CH)
COFAEN:
to change the frame alignment position. The one bit deletion or repetition occurs randomly.
TXDIS:
TAIS:
E1 FGEN Interrupt Control (06DH, 16DH, 26DH, 36DH, 46DH, 56DH, 66DH, 76DH)
SMFE:
FASE:
SIGMFE:
MFE:
BFE:
Programming Information
IDT82P2288
Bit Name
Bit Name
Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on this bit will lead to one bit deletion or one bit repetition in the data stream to be transmitted, that is,
= 0: Normal operation.
= 1: The data stream to be transmitted is overwritten with all ‘Zero’s.
= 0: Normal operation.
= 1: The data stream to be transmitted is overwritten with all ‘One’s.
= 0: Disable the interrupt on the INT pin when the SMFI bit (b4, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SMFI bit (b4, E1-06EH,...) is ‘1’.
= 0: Disable the interrupt on the INT pin when the FASI bit (b3, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the FASI bit (b3, E1-06EH,...) is ‘1’.
= 0: Disable the interrupt on the INT pin when the SIGMFI bit (b2, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the SIGMFI bit (b2, E1-06EH,...) is ‘1’.
= 0: Disable the interrupt on the INT pin when the MFI bit (b1, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the MFI bit (b1, E1-06EH,...) is ‘1’.
= 0: Disable the interrupt on the INT pin when the BFI bit (b0, E1-06EH,...) is ‘1’.
= 1: Enable the interrupt on the INT pin when the BFI bit (b0, E1-06EH,...) is ‘1’.
Default
Default
Bit No.
Bit No.
Type
Type
7
7
Reserved
6
6
Reserved
5
5
SMFE
R/W
4
4
0
291
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
FASE
R/W
3
3
0
COFAEN
SIGMFE
R/W
R/W
2
0
2
0
TXDIS
MFE
R/W
R/W
1
0
1
0
March 04, 2009
TAIS
R/W
BFE
R/W
0
0
0
0