CS5461A-ISR Cirrus Logic Inc, CS5461A-ISR Datasheet - Page 21
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CS5461A-ISR
Manufacturer Part Number
CS5461A-ISR
Description
Other Power Management IC Sngl-Phs BiDirect PWR/Energy
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5461A-ISZ.pdf
(44 pages)
Specifications of CS5461A-ISR
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
dal inputs so there are no problems with slow edge
times.
The CS5461A can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
then DCLK is 3 MHz, which is a valid value for DCLK.
5.12 Event Handler
The INT pin is used to indicate that an internal error or
event has taken place in the CS5461A. Writing a logic 1
to any bit in the Mask Register allows the corresponding
bit in the Status Register to activate the INT pin. The in-
terrupt condition is cleared by writing a logic 1 to the bit
that has been set in the Status Register.
The behavior of the INT pin is controlled by the IMODE
and IINV bits of the Configuration Register.
DS661F2
IMODE
0
0
1
Table 3. Interrupt Configuration
IINV
0
1
0
Active-high Level
Active-low Level
Low Pulse
INT Pin
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK/K).
5.12.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
IMODE
1) All Status bits are cleared by writing 0xFFFFFF to
2) The condition bits which will be used to generate
3) Enable interrupts.
4) Read the Status Register.
5) Disable all interrupts.
6) Branch to the proper interrupt service routine.
7) Clear the Status Register by writing back the read
8) Re-enable interrupts.
9) Return from interrupt service routine.
INITIALIZATION:
INTERRUPT HANDLER ROUTINE:
1
the Status Register.
interrupts are then set to logic 1 in the Mask Reg-
ister.
value in step 4.
Table 3. Interrupt Configuration
IINV
1
High Pulse
INT Pin
CS5461A
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