CAT1163P-28 Catalyst / ON Semiconductor, CAT1163P-28 Datasheet - Page 9

• Manufacturer Part Number: CAT1163P-28
• Description: Supervisory Circuits 16K I2C Memory w/WDT
• Manufacturer: Catalyst / ON Semiconductor

Specifications of CAT1163P-28

• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Output Type: Active High, Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Minimum Operating Temperature: 0 C
• Power Fail Detection: No
• Undervoltage Threshold: 2.85 V
• Overvoltage Threshold: 3 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1163 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the CAT1163 is still busy with the write operation, no
ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to
protect against inadvertent memory array program-
ming. If the WP pin is tied to V
array is protected and becomes read only. The
CAT1163 will accept both slave and byte addresses,
but the memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Figure 9. Immediate Address Read Timing
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
SDA
SCL
BUS ACTIVIT Y:
CC
SDA LINE
MASTER
, the entire memory
DATA OUT
8TH BI T
8
S
S
A
R
T
T
ADDRESS
SLAVE
9
READ OPERATIONS
The READ operation for the CAT1163 is initiated in the
same manner as the write operation with one exception,
that R/W ¯ ¯ bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ, Selective/Random READ and Sequential READ.
Immediate/Current Address Read
The CAT1163’s address counter contains the address
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
address N, the READ immediately following would
access data from address N + 1. If N = E (where = 2047
for the CAT1163) then the counter will ’wrap around’ to
address 0 and continue to clock out data. After the
CAT1163 receives its slave address information (with
the R/W ¯ ¯ bit set to one), it issues an acknowledge, then
transmits the 8-bit byte requested. The master device
does not send an acknowledge, but will generate a
STOP condition.
9
C
A
K
NO ACK
DATA
O
N
A
C
K
P
S
O
P
T
STOP
Doc. No. MD-3003 Rev. I
CAT1163