NCP346SN2T1G ON Semiconductor, NCP346SN2T1G Datasheet - Page 2

• Manufacturer Part Number: NCP346SN2T1G
• Description: Supervisory Circuits 5.5V Overvoltage Supervisor
• Manufacturer: ON Semiconductor

Specifications of NCP346SN2T1G

• Number Of Voltages Monitored: 1
• Monitored Voltage: 5.5 V
• Overvoltage Threshold: Adjustable, 4.55 V
• Output Type: PFET Driver
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 25 V
• Supply Voltage (min): 2.5 V
• Supply Current (typ): 650 uA
• Maximum Power Dissipation: 216 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23-5 Thin (TSOP-5)
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIN FUNCTION DESCRIPTIONS
TRUTH TABLE
Pin #
1
2
3
4
5
<V
<V
>V
>V
IN
th
th
th
th
Symbol
CNTRL
CNTRL
OUT
GND
V
IN
CC
(4)
IN
(3)
This signal drives the gate of a P−channel MOSFET. It is controlled by the voltage level on IN or the logic state of
the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of V
than 1.0 msec provided that gate and stray capacitance is less than 12 nF.
Circuit Ground
This logic signal is used to control the state of OUT and turn−on/off the P−channel MOSFET. A logic High results
in the OUT signal being driven to within 1.0 V of V
internal 50 kW pull−down resistor. It is recommended that the input be connected to GND if it is not used.
This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold (V
the OUT pin will be driven to within 1.0 V of V
increased with the addition of an external resistor divider between IN, V
Positive Voltage supply. OUT is guaranteed to be in low state (MOSFET ON) as long as V
2.5 V, and below the overvoltage threshold.
R1
R2
CNTRL
H
H
L
L
Reference
Bandgap
Pre−regulator
V
CC
V5
Figure 2. Detailed Block Diagram
GND
OUT
V
V
V
CC
CC
CC
http://onsemi.com
+
−
COMP
NCP346
2
CC
GND
(2)
V
(5)
, thus disconnecting the FET. The nominal threshold level can be
CC
Pin Description
CC
which disconnects the FET. The input is tied Low via an
BLOCK
LOGIC
CC
ON/OFF
, and GND.
DRIVER
V
CC
OUT
CC
remains above
OUT
(1)
CC
in less
th
),