CAT150089SWI-G ON Semiconductor, CAT150089SWI-G Datasheet - Page 7

• Manufacturer Part Number: CAT150089SWI-G
• Description: Supervisory Circuits w/8k SPI
• Manufacturer: ON Semiconductor

Specifications of CAT150089SWI-G

• Number Of Voltages Monitored: 1
• Monitored Voltage: 2.5 V, 3 V, 3.3 V, 5 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Supply Current (typ): 2000 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
The RDY
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the
user with the WRSR command and are non-volatile. The
Table 2. Status Register
Table 3. Block Protection Bits
Table 4. Write Protect Enable Operation
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
Status Register Bits
WPEN
BP1
WPEN
¯¯¯¯ (Ready) bit indicates whether the device is
X
X
0
0
1
1
0
0
1
1
7
High
High
Low
Low
BP0
¯¯¯
WP
X
X
0
1
0
1
6
0
Array Address Protected
None
15008: 0300-03FF
15016: 0600-07FF
15008: 0200-03FF
15016: 0400-07FF
15008: 0000-03FF
15016: 0000-07FF
WEL
0
1
0
1
0
1
5
0
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
4
0
7
user is allowed to protect a quarter, one half or the entire
memory, by setting these bits according to Table 3. The
protected blocks then become read-only.
The WPEN (Write Protect Enable) bit acts as an enable
for the WP
when the WP
condition prevents writing to the status register and to
the block protected sections of memory. While
hardware write protection is active, only the non-block
protected memory can be written. Hardware write
protection is disabled when the WP
WPEN bit is 0. The WPEN bit, WP
combine to either permit or inhibit Write operations, as
detailed in Table 4.
BP1
3
Unprotected Blocks
¯¯¯ pin. Hardware write protection is enabled
¯¯¯ pin is low and the WPEN bit is 1. This
Protected
Protected
Protected
Quarter Array Protection
Writable
Writable
Writable
Half Array Protection
Full Array Protection
BP0
No Protection
2
Protection
CAT15008, CAT15016
WEL
¯¯¯ pin is high or the
¯¯¯ pin and WEL bit
1
Status Register
Protected
Protected
Protected
Protected
Writable
Writable
Doc. No. MD-1125 Rev. B
¯¯¯¯
RDY
0