ispPAC-POWR607-01NN32I Lattice, ispPAC-POWR607-01NN32I Datasheet - Page 15

• Manufacturer Part Number: ispPAC-POWR607-01NN32I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. I
• Manufacturer: Lattice

Specifications of ispPAC-POWR607-01NN32I

• Number Of Voltages Monitored: 6
• Undervoltage Threshold: 0.8 V
• Output Type: Open Collector / Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Power-up Reset Delay (typ): 300 us
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.64 V
• Supply Current (typ): 3.5 mA
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 4-11. ispPAC-POWR607 Macrocell Block Diagram
Clock and Timer Functions
Figure 4-12 shows a block diagram of the ispPAC-POWR607’s internal clock and timer systems. The master clock
operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived.
Figure 4-12. Clock and Timer System
The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer
clocks. It is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir-
cuits.
A divide-by-32 prescaler divides the internal 8MHz oscillator down to 250kHz for the PLD clock and for the pro-
grammable timers. Each of the four timers provides independent timeout intervals ranging from 32µs to 1.96 sec-
onds in 128 steps.
PT4
PT3
PT2
PT1
PT0
Clock
Polarity
Block Init Product Term
Oscillator
Internal
8MHz
Global Polarity Fuse for
Init Product Term
Product Term Allocation
32
Power On Reset
4-15
Timer 0
Timer 1
Timer 2
Timer 3
Macrocell flip-flop provides
D, T, or combinatorial
ispPAC-POWR607 Data Sheet
output with polarity
PLD Clock
D/T
To/From
R
CLK
PLD
P
Q
To PLD Output