SC403MLTRT Semtech, SC403MLTRT Datasheet - Page 28

• Manufacturer Part Number: SC403MLTRT
• Manufacturer: Semtech

Specifications of SC403MLTRT

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Applications Information (continued)
PCB Layout Guidelines
The optimum layout for the SC403 is shown in Figure 15.
This layout shows an integrated FET buck regulator with a
maximum current of 6A. The total PCB area is approxi-
mately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
IC Decoupling Capacitors
•
•
•
•
•
•
•
IC decoupling capacitors
PGND plane
AGND island
FB, VOUT, and other analog control signals
BST, ILIM, and LX
CIN and COUT placement and current loops
A 0.1 μF capacitor must be located as close as
possible to the IC and directly connected to pins
3 (VDD) and 4 (AGND).
Top Layer
PGND on
VOUT Plane
on Top layer
shown Top Side
All components
AGND plane on
V5V Decoupling Capacitor
inner layer
PGND
C
RLDO2
OUT
RFB1
CFF
Figure 15 — PCB Layout
RLDO1
RGND — AGND connects to
PGND close to the IC
CLDO
RFB2
C
PGND Plane
IN
L
•
•
•
•
•
RGND
All other decoupling capacitors must be located
as close as possible to the IC.
PGND requires its own copper plane with no
other signal traces routed on it.
Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the
device.
The PGND copper area between the input
capacitors, output capacitors, and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
Connect PGND to AGND with a short trace or
0Ω resistor. This connection should be as close
to the device as possible.
RILIM
Pin 1 marking
LX plane on inner
LX, AGND, VIN
IC with vias for
V
or bottom layer
PGND on inner
or bottom layer
or bottom layer
IN
plane on inner
SC403
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