PDLXT310NE.D4 Intel, PDLXT310NE.D4 Datasheet - Page 13

• Manufacturer Part Number: PDLXT310NE.D4
• Manufacturer: Intel

Specifications of PDLXT310NE.D4

• Number Of Line Interfaces: 1
• Lead Free Status / Rohs Status: Not Compliant

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2.5.2
Datasheet
SDI/ SDO
SCLK
CS
ADDRESS /
COMMAND
BYTE
INPUT
DATA
BYTE
Figure 5. LXT310 Serial Interface Data Structure
Table 3. LXT310 Serial Data Output Bits (See Figure 5)
R/W
CLEAR INTERRUPTS
R/W
D0 (LSB)
Hardware Mode Operation
In Hardware mode the transceiver is accessed and controlled through individual pins. With the
exception of the INT and CLKE functions, Hardware mode provides all the functions provided in
the Host mode. In the Hardware mode RPOS/RNEG or RDATA outputs are valid on the rising
edge of RCLK. The LXT310 operates in Hardware mode only when MODE is set Low or
connected to RCLK.
LOS
Bit
D5
A0
0
0
0
0
1
1
1
1
A0
0
Bit
D6
A1
0
0
1
1
0
0
1
1
ADDRESS / COMMAND BYTE
1=ENABLE
NLOOP
0
Bit
D7
A2
0
1
0
1
0
1
0
1
Reset has occurred, or no program input.
TAOS is active.
Local Loopback is active.
TAOS and Local Loopback are active.
Remote Loopback is active.
DPM has changed state since last Clear
DPM occurred.
LOS has changed state since last Clear
LOS occurred.
LOS and DPM have both changed state
since last Clear DPM and Clear LOS
occurred.
A3
0
1=ENABLE
B8ZS
A4
0
LBO1
A5
A4
1
Status
A6
X=DON’T CARE
0
LBO2
D0
A6
X
T1 CSU/ISDN PRI Transceiver — LXT310
D1
1=ENABLE
SET DIAGNOSTICS OR RESET
RLOOP
R/W- = 1: Read
R/W- = 0: Write
DATA INPUT / OUTPUT BYTE
D2
1=ENABLE
D3
LLOOP
D4
1=ENABLE
D7(MSB)
D5
NOTE:
Output data byte is
the same as the input
data byte except for
bits D<5:7> shown in
Table
TAOS
3.
D6
D7
13