MAX97236EVKIT+ Maxim Integrated Products, MAX97236EVKIT+ Datasheet - Page 32

• Manufacturer Part Number: MAX97236EVKIT+
• Description: Audio Modules & Development Tools MAX97236 Eval Kit
• Manufacturer: Maxim Integrated Products

Specifications of MAX97236EVKIT+

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Audio Amplifier with Jack Detection
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write bit. The IC has an
address of 0x80. The 7 most significant bits are 100000.
Setting the read/write bit to 1 (slave address = 0x81)
configures the IC for read mode. Setting the read/write
bit to 0 (slave address = 0x80) configures the IC for write
mode. The address is the first byte of information sent to
the IC after the START condition.
The acknowledge bit (ACK) is a clocked ninth bit that the
IC uses to handshake receipt each byte of data when
in write mode
ing the entire master-generated ninth clock pulse if the
previous byte is successfully received. Monitoring ACK
32
Figure 12. Acknowledge
Figure 13. Writing One Byte of Data to the IC
Figure 14. Writing n Bytes of Data to the IC
SCL
SDA
CONDITION
START
S
S
SLAVE ADDRESS
ACKNOWLEDGE FROM
(Figure
1
ACKNOWLEDGE FROM MAX97236
SLAVE ADDRESS
MAX97236
2
12). The IC pulls down SDA dur-
R/W
0
A
NOT ACKNOWLEDGE
R/W
ACKNOWLEDGE
0
REGISTER ADDRESS
ACKNOWLEDGMENT
8
ACKNOWLEDGE FROM
CLOCK PULSE FOR
A
Slave Address
Acknowledge
MAX97236
9
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX97236
REGISTER ADDRESS
A
B7 B6
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master retries com-
munication. The master pulls down SDA during the 9th
clock cycle to acknowledge receipt of data when the IC
is in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue. A
not-acknowledge is sent when the master reads the final
byte of data from the IC, followed by a STOP condition.
A write to the IC includes transmission of a START condi-
tion, the slave address with the R/W bit set to 0, one byte of
data to configure the internal register address pointer, one
or more bytes of data, and a STOP condition.
illustrates the proper frame format for writing one byte of
data to the IC.
writing n bytes of data to the IC.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the IC. The IC
acknowledges receipt of the address byte during the
master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the IC’s internal register address pointer. The pointer
tells the IC where to write the next byte of data. An
acknowledge pulse is sent by the IC upon receipt of the
address pointer data.
ACKNOWLEDGE FROM
B5 B4
DATA BYTE 1
1 BYTE
B3 B2
MAX97236
B1 B0
A
Figure 14
B7
A
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
B6
ACKNOWLEDGE FROM MAX97236
B5
B7 B6
illustrates the frame format for
DATA BYTE
B4
1 BYTE
ACKNOWLEDGE FROM
B5 B4
B3
DATA BYTE n
1 BYTE
B2
B3 B2
MAX97236
Write Data Format
B1
B1 B0
B0
A
A
Figure 13
P
P