APA-EVAL-KIT MICROSEMI, APA-EVAL-KIT Datasheet - Page 57
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APA-EVAL-KIT
Manufacturer Part Number
APA-EVAL-KIT
Description
MCU, MPU & DSP Development Tools ProAsic Plus Eval Kit
Manufacturer
MICROSEMI
Datasheet
1.APA075-FGG144.pdf
(178 pages)
Specifications of APA-EVAL-KIT
Processor To Be Evaluated
APA
Interface Type
ISP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 2-37 • Worst-Case Military Conditions
Table 2-38 • Worst-Case Military Conditions
Macro Type
IB33
IB33S
Notes:
1. t
2. t
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, V
Macro Type
IB25LP
IB25LPS
Notes:
1. t
2. t
3. LVTTL delays are the same as CMOS delays.
4. For LP Macros, V
INYH
INYL
INYH
INYL
= Input Pad-to-Y Low
= Input Pad-to-Y Low
= Input Pad-to-Y High
= Input Pad-to-Y High
V
V
DDP
DDP
Description
3.3 V, CMOS Input Levels
3.3 V, CMOS Input Levels
Description
2.5 V, CMOS Input Levels
2.5 V, CMOS Input Levels
= 3.0V, V
= 2.3V, V
DDP
DDP
= 2.3 V for delays.
= 2.3 V for delays.
DD
DD
= 2.3V, T
= 2.3V, T
J
J
= 125°C for Military/MIL-STD-883
= 125°C for Military/MIL-STD-883
3
3
3
3
, No Pull-up Resistor
, No Pull-up Resistor, Schmitt Trigger
, Low Power
, Low Power, Schmitt Trigger
v5.9
Max. t
Max. t
Std.
Std.
0.5
0.6
0.9
0.8
INYH
INYH
ProASIC
1
1
PLUS
Max. t
Max. t
Std.
Std.
Flash Family FPGAs
0.6
0.8
0.7
1.0
INYL
INYL
2
2
Units
Units
ns
ns
ns
ns
2-47
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