K4S560832E-NC75 Samsung Semiconductor, K4S560832E-NC75 Datasheet - Page 3

• Manufacturer Part Number: K4S560832E-NC75
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S560832E-NC75

• Organization: 32Mx8
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 100mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

SDRAM 256Mb E-die (x4, x8, x16)
SDRAM 256Mb E-die (x4, x8, x16)
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
•
• RoHS compliant
GENERAL DESCRIPTION
16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchro-
nous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of oper-
ating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
Ordering Information
The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
54 TSOP(II) Pb-free Package
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
K4S561632E-UC(L)60/75
K4S560432E-UC(L)75
K4S560832E-UC(L)75
Part No.
Organization
16Mx16
64Mx4
32Mx8
Row & Column address configuration
Orgainization
16M x 16
64M x 4
32M x 8
Row Address
A0~A12
A0~A12
A0~A12
Max Freq.
133MHz
133MHz
133MHz
Column Address
A0-A9, A11
A0-A9
A0-A8
Interface
LVTTL
LVTTL
LVTTL
Rev. 1.3 August 2004
CMOS SDRAM
54pin TSOP(II)
54pin TSOP(II)
54pin TSOP(II)
Package