CY7C4292-15ASC Cypress Semiconductor Corp, CY7C4292-15ASC Datasheet - Page 11

• Manufacturer Part Number: CY7C4292-15ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4292-15ASC

• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 128Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 40mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06009 Rev. *B
Switching Waveforms
Note:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. For standalone or width expansion configuration only.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
19. When t
20. The first word is available the cycle after EF goes HIGH, always.
REN, WEN
First Data Word Latency after Reset with Simultaneous Read and Write
Reset Timing
Q
D
Q
0
0
EF,PAE
FF,PAF
WCLK
The Latency Timing applies only at the Empty Boundary (EF = LOW).
0 –
RCLK
WEN
–D
–Q
REN
OE
RS
EF
LD
Q
8
8
8
[17]
SKEW1
t
ENS
> minimum specification, t
[16]
t
DS
D
0
(FIRSTVALID WRITE)
(continued)
FRL
(maximum) = t
t
SKEW1
t
t
t
t
RSS
RSF
RSF
RSF
t
RS
t
OLZ
t
FRL
CLK
[19]
+ t
SKEW2
t
. When t
REF
D
1
SKEW1
t
< minimum specification, t
OE
t
RSR
t
D
A
2
FRL
(maximum) = either 2*t
D
0
t
A
[20]
D
3
CLK
+ t
OE=1
OE=0
CY7C4282
CY7C4292
SKEW1
[18]
Page 11 of 16
or t
CLK
D
4282–9
+ t
1
D
SKEW1
4
.
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