LM70CIMMX-5/HALF National Semiconductor, LM70CIMMX-5/HALF Datasheet - Page 5

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LM70CIMMX-5/HALF

Manufacturer Part Number
LM70CIMMX-5/HALF
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of LM70CIMMX-5/HALF

Lead Free Status / Rohs Status
Supplier Unconfirmed
t
t
t
t
t
t
t
1
2
3
4
5
6
7
Symbol
Logic Electrical Characteristics
Serial Bus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
LM70-5, C
to T
Timing Diagrams
MAX
; all other limits T
L
SC (Clock) Period
CS Low to SC (Clock) High Set-Up Time
CS Low to Data Out (SO) Delay
SC (Clock) Low to Data Out (SO) Delay
CS High to Data Out (SO) TRI-STATE
SC (Clock) High to Data In (SI) Hold Time
Data In (SI) Set-Up Time to SC (Clock) High
(load capacitance) on output lines = 100 pF unless otherwise specified. Boldface limits apply for T
A
= T
J
= +25˚C, unless otherwise noted.
Parameter
FIGURE 3. TRI-STATE Data Output Timing Diagram
FIGURE 2. Data Output Timing Diagram
FIGURE 4. Data Input Timing Diagram
(Continued)
+
= 2.65V to 3.6V for the LM70-3 and V
5
Conditions
10122304
(Note 7)
Typical
10122306
10122305
+
= 4.5V to 5.5V for the
(Note 8)
Limits
0.16
100
200
DC
70
70
60
30
A
= T
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J
ns (max)
ns (max)
µs (min)
ns (min)
ns (min)
ns (min)
ns (min)
(Limit)
= T
Units
(max)
MIN