Si5327-EVB Silicon Laboratories Inc, Si5327-EVB Datasheet - Page 50

• Manufacturer Part Number: Si5327-EVB
• Description: MCU, MPU & DSP Development Tools SI5327 EVAL BOARD
• Manufacturer: Silicon Laboratories Inc

Specifications of Si5327-EVB

• Processor To Be Evaluated: Si5327
• Interface Type: I2C, SPI
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: Details

Si5327
50
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
5, 10, 32
8, 15, 31
Pin #
11
16
17
12
13
4
7
6
Pin Name
CKIN1+
CKIN1–
CKIN2+
CKIN2–
LOS2
RATE
GND
V
XB
XA
DD
GND
V
I/O
O
DD
I
I
I
I
Signal Level
LVCMOS
3-Level
Supply
Analog
Supply
Multi
Multi
CKIN2 Invalid Indicator.
This pin functions as a LOS alarm indicator for CKIN2 if
CK2_BAD_PIN = 1.
0 = CKIN2 present
1 = LOS on CKIN2
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capac-
itors should be associated with the following V
5
10
32
A 1.0 µF should also be placed as close to the device as is practical.
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. Refer to the Si53xx Family Reference
Manual for interfacing to an external reference. External reference
must be from a high-quality clock source (TCXO, OCXO). Accepts
37–41 MHz crystal or reference clock, as determine by the RATE
pin setting.
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device. Grounding these
pins does not eliminate the requirement to ground the GND PAD on
the bottom of the package.
External Crystal or Reference Clock Rate.
Three level input that selects an external crystal or reference clock
to be applied to the XA/XB interface.
L setting (GND) = crystal on XA/XB
M setting (VDD/2) = clock or XO on XA/XB
H setting (VDD) = reserved
Some designs may require an external resistor voltage divider when
driven by an active device that will tristate.
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
Preliminary Rev. 0.4
0.1 µF
0.1 µF
0.1 µF
Description
DD
pins: