AD80066KRSZ Analog Devices Inc, AD80066KRSZ Datasheet
AD80066KRSZ
Specifications of AD80066KRSZ
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AD80066KRSZ Summary of contents
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FEATURES 16-bit, 24 MSPS analog-to-digital converter (ADC) 4-channel operation MHz (6 MHz/channel) 3-channel operation MHz (8 MHz/channel) Selectable input range 1.5 V peak-to-peak Input clamp circuitry Correlated double sampling 1×~6× programmable ...
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AD80066 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Analog Specifications ................................................................... 3 Digital Specifications ................................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum ...
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SPECIFICATIONS ANALOG SPECIFICATIONS AVDD = 5 V, DRVDD = 5 V, CDS mode, f MIN MAX Table 1. Parameter MAXIMUM CONVERSION RATE 4-Channel Mode with CDS 3-Channel Mode with CDS 2-Channel Mode with CDS 1-Channel Mode ...
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AD80066 Parameter POWER DISSIPATION 4-Channel Mode at 24 MHz 1-Channel Mode at 12 MHz 4-Channel Mode at 8 MHz, Slow Power Mode 1 The linear input signal range p-p when the CCD reference level is ...
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TIMING SPECIFICATIONS AVDD = 5 V, DRVDD = 5 V. MIN MAX Table 3. Parameter CLOCK PARAMETERS 4-Channel Pixel Rate 1-Channel Pixel Rate ADCCLK Pulse Width CDSCLK1 Pulse Width CDSCLK2 Pulse Width 1 CDSCLK1 Falling to ...
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AD80066 PIXEL n ( ANALOG t INPUTS CDSCLK1 t C1C2 CDSCLK2 t ADCCLK ADCCLK OUTPUT DATA A(n – 2) B(n – 2) B(n – 2) C(n – 2) C(n – 2) A(n – 1) A(n ...
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PIXEL n ANALOG t INPUTS CDSCLK1 t C1C2 CDSCLK2 t C2ADR ADCCLK t ADCCLK OUTPUT DATA PIXEL (n – 4) PIXEL (n – 4) (D[7:0]) LOW HIGH BYTE BYTE NOTES 1. IN 1-CHANNEL CDS MODE. THE CDSCLK1 ...
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AD80066 ANALOG INPUTS CDSCLK2 t ADCCLK t ADCCLK OUTPUT PIXEL (n – 4) PIXEL (n – 4) DATA (D[7:0]) HIGH BYTE LOW BYTE ADCCLK OUTPUT DATA HIGH BYTE (D[7:0]) (DB[15:8]) PIXEL n ADCCLK t OD OUTPUT DATA HIGH BYTE (D[7:0]) ...
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ABSOLUTE MAXIMUM RATINGS Table 4. Parameter With Respect To VINx, CAPT, CAPB AVSS Digital Inputs AVSS SDATA DRVSS AVDD AVSS DRVDD DRVSS AVSS DRVSS Digital Outputs DRVSS (D[7:0]) Temperature Junction Storage Lead (10 sec) Stresses above those listed under Absolute ...
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AD80066 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic Type 1 AVDD P 2 CDSCLK1 DI 3 CDSCLK2 DI 4 ADCCLK DI 5 DRVDD P 6 DRVSS (MSB ...
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TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.5 0 –0.5 –1.0 0 12,800 25,600 38,400 ADC OUTPUT CODE Figure 14. Typical DNL Performance PGA REGISTER VALUE (Decimal) Figure 15. ...
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AD80066 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. The point used as zero scale occurs ½ LSB before the first code ...
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THEORY OF OPERATION The AD80066 can be operated in several different modes, including 4-channel CDS mode, 4-channel SHA mode, 1-channel CDS mode, and 1-channel SHA mode. Each mode is selected by programming the configuration register through the serial interface. For ...
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AD80066 INTERNAL REGISTER MAP Table 7. Internal Register Map Address Register Name Configuration Mux Gain Gain Gain C ...
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INTERNAL REGISTER DETAILS CONFIGURATION REGISTER The configuration register controls the AD80066 operating mode and bias levels. The D8, D7, and D6 bits should always be set low. Bit D2 sets the full-scale input voltage range of the AD80066 ADC to ...
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AD80066 Table 11. Offset Register Settings (MSB … … … … … … … … 1 ...
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CIRCUIT OPERATION ANALOG INPUTS—CDS MODE Figure 17 shows the analog input configuration for the CDS mode of operation. Figure 18 shows the internal timing for the sampling switches. The CCD reference level is sampled when CDSCLK1 transitions from high to ...
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AD80066 ANALOG INPUTS—SHA MODE Figure 19 shows the analog input configuration for the SHA mode of operation. Figure 20 shows the internal timing for the sampling switches. The input signal is sampled when CDSCLK2 transitions from high to low, opening ...
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APPLICATIONS INFORMATION CIRCUIT AND LAYOUT RECOMMENDATIONS Figure 23 shows the recommended circuit configuration for 4-channel CDS mode operation. The recommended input coupling capacitor value is 0.1 μF (see the Analog Inputs—CDS Mode section). A single ground plane is recommended for ...
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... MAX 0.05 MIN COPLANARITY 0.10 ORDERING GUIDE 1 Model Temperature Range AD80066KRSZ 0°C to 70°C AD80066KRSZRL 0°C to 70° RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 10.50 10.20 9. ...