AD5755-1ACPZ Analog Devices Inc, AD5755-1ACPZ Datasheet - Page 37

• Manufacturer Part Number: AD5755-1ACPZ
• Description: 16Bit Quad,V/I DAC No Dynamic Power Ctrl
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of AD5755-1ACPZ

• Input Channel Type: Serial
• Data Interface: 3-Wire, Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +105°C
• Rohs Compliant: Yes
• Resolution (bits): 16bit
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Featured Product: AD5755 / AD5755-1 / AD5757 DACs
• Settling Time: 11µs
• Number Of Bits: 16
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): -
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 64-VFQFN Exposed Pad, CSP
• Number Of Outputs And Type: 4 Current, 4 Voltage
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Slew Rate Control Register
This register is used to program the slew rate control for the
selected DAC channel. This feature is available on both the
current and voltage outputs. The slew rate control is enabled/
disabled and programmed on a per channel basis. See Table 26
and the Digital Slew Rate Control section for more information.
READBACK OPERATION
Readback mode is invoked by setting the R/ W bit = 1 in the
serial input register write. See
with a readback operation. The DUT_AD1 and DUT_AD0 bits,
in association with Bits RD[4:0], select the register to be read.
The remaining data bits in the write sequence are don’t cares.
During the next SPI transfer (see
on the SDO output contains the data from the previously
Table 26. Programming the Slew Rate Control Register
D15
0
1
Table 27. Input Shift Register Contents for a Read Operation
D23
R/W
1
Table 28. Read Address Decoding
RD4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
X = don’t care.
X = don’t care.
D22
DUT_AD1
RD3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
D14
0
Table 27
D13
0
D21
DUT_AD0
RD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
Figure 4
for the bits associated
), the data appearing
D20
RD4
D12
SE
RD1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Rev. A | Page 37 of 48
D11 to D7
X
D19
RD3
RD0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
addressed register. This second SPI transfer should either be a
request to read yet another register on a third data transfer or
0x1CE000, which is the no operation command.
Readback Example
To read back the gain register of Device 1, Channel A on the
AD5755-1, implement the following sequence:
1.
2.
D18
RD2
Read DAC A data register
Read DAC B data register
Read DAC C data register
Read DAC D data register
Read DAC A control register
Read DAC B control register
Read DAC C control register
Read DAC D control register
Read DAC A gain register
Read DAC B gain register
Read DAC C gain register
Read DAC D gain register
Read DACA offset register
Read DAC B offset register
Read DAC C offset register
Read DAC D offset register
Clear DAC A code register
Clear DAC B code register
Clear DAC C code register
Clear DAC D code register
DAC A slew rate control register
DAC B slew rate control register
DAC C slew rate control register
DAC D slew rate control register
Read status register
Read main control register
Read dc-to-dc control register
Function
Write 0xA80000 to the AD5755-1 input register. This
configures the AD5755-1 Device Address 1 for read mode
with the gain register of Channel A selected. All the data
bits, D15 to D0, are don’t cares.
Follow with another read command or a no operation
command (0x1CE000). During this command, the data
from the Channel A gain register is clocked out on the
SDO line.
D17
RD1
D6 to D3
SR_CLOCK
D16
RD0
D15 to D0
X
D2 to D0
SR_STEP
1
AD5755-1