PIC32MX460F256LT-80V/PT Microchip Technology, PIC32MX460F256LT-80V/PT Datasheet - Page 143

• Manufacturer Part Number: PIC32MX460F256LT-80V/PT
• Description: 256 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 100 TQFP 12x12x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F256LT-80V/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP
• Core: MIPS
• Processor Series: PIC32MX4xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 80 MHz
• Data Ram Size: 32 KB
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Mounting Style: SMD/SMT
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Operating Temperature: + 105 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 27-1:
© 2011 Microchip Technology Inc.
JAL
JALR
JALR.HB
JR
JR.HB
LB
LBU
LH
LHU
LL
LUI
LW
LWPC
LWL
LWR
MADD
MADDU
MFC0
MFHI
MFLO
MOVN
MOVZ
MSUB
MSUBU
MTC0
MTHI
MTLO
MUL
MULT
MULTU
NOP
NOR
OR
ORI
RDHWR
Note 1:
Instruction
This instruction is deprecated and should not be used.
MIPS32
Jump and Link
Jump and Link Register
Jump and Link Register with Hazard Barrier
Jump Register
Jump Register with Hazard Barrier
Load Byte
Unsigned Load Byte
Load Halfword
Unsigned Load Halfword
Load Linked Word
Load Upper Immediate
Load Word
Load Word, PC relative
Load Word Left
Load Word Right
Multiply-Add
Multiply-Add Unsigned
Move from Coprocessor 0
Move from HI
Move from LO
Move Conditional on Not Zero
Move Conditional on Zero
Multiply-Subtract
Multiply-Subtract Unsigned
Move to Coprocessor 0
Move to HI
Move to LO
Multiply with register write
Integer Multiply
Unsigned Multiply
No Operation
(Assembler idiom for: SLL r0, r0, r0)
Logical NOR
Logical OR
Logical OR Immediate
Read Hardware Register (if enabled by HWRE
Register)
®
INSTRUCTION SET (CONTINUED)
Description
na
PIC32MX3XX/4XX
GPR[31] = PC + 8
PC = PC[31:28] || offset<<2
Rd = PC + 8
PC = Rs
Like JALR, but also clears execution and
instruction hazards
PC = Rs
Like JR, but also clears execution and
instruction hazards
Rt = (byte)Mem[Rs+offset]
Rt = (ubyte))Mem[Rs+offset]
Rt = (half)Mem[Rs+offset]
Rt = (uhalf)Mem[Rs+offset]
Rt = Mem[Rs+offset>
LL
LLAdr = Rs + offset
Rt = immediate << 16
Rt = Mem[Rs+offset]
Rt = Mem[PC+offset]
Re = Re MERGE Mem[Rs+offset]
Re = Re MERGE Mem[Rs+offset]
HI | LO += (int)Rs * (int)Rt
HI | LO += (uns)Rs * (uns)Rt
Rt = CPR[0, Rd, sel]
Rd = HI
Rd = LO
if Rt ¼ 0 then
if Rt = 0 then
HI | LO -= (int)Rs * (int)Rt
HI | LO -= (uns)Rs * (uns)Rt
CPR[0, n, Sel] = Rt
HI = Rs
LO = Rs
HI | LO =Unpredictable
Rd = ((int)Rs * (int)Rt)
HI | LO = (int)Rs * (int)Rd
HI | LO = (uns)Rs * (uns)Rd
Rd = ~(Rs | Rt)
Rd = Rs | Rt
Rt = Rs | Immed
Re = HWR[Rd]
bit
Rd = Rs
Rd = Rs
= 1
Function
DS61143H-page 143
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