STM32W108HBU64TR STMicroelectronics, STM32W108HBU64TR Datasheet - Page 96
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
STM32W108HBU64TR
Manufacturer Part Number
STM32W108HBU64TR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32W108B-KEXT.pdf
(209 pages)
Specifications of STM32W108HBU64TR
Applications
RF4CE, Remote Control
Core Processor
ARM® Cortex-M3™
Program Memory Type
FLASH (128 kB)
Controller Series
STM32W
Ram Size
8K x 8
Interface
I²C, SPI, UART/USART
Number Of I /o
18
Voltage - Supply
1.18 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32W108HBU64TR
Manufacturer:
TDK
Quantity:
30 000
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Serial interfaces
9.12
9.12.1
9.12.2
96/209
31
15
31
15
30
14
30
14
Universal asynchronous receiver / transmitter (UART)
registers
Refer to the SPI Master mode section for a description of the SCx_DATA register.
UART status register (SC1_UARTSTAT)
Address offset: 0xC848
Reset value:
UART configuration register (SC1_UARTCFG)
Address offset: 0xC85C
Reset value:
Bit 6 SC_UARTTXIDLE: This bit is set when both the transmit FIFO and the transmit serializer are
Bit 5 SC_UARTPARERR: This bit is set when the byte in the data register was received with a parity
Bit 4 SC_UARTFRMERR: This bit is set when the byte in the data register was received with a frame
Bit 3 SC_UARTRXOVF: This bit is set when the receive FIFO has been overrun. This occurs if a byte
Bit 2 SC_UARTTXFREE: This bit is set when the transmit FIFO has space for at least one byte.
Bit 1 SC_UARTRXVAL: This bit is set when the receive FIFO contains at least one byte.
Bit 0 SC_UARTCTS: This bit is set when both the transmit FIFO and the transmit serializer are
29
13
29
13
empty.
error. This bit is updated when the data register is read, and is cleared if the receive FIFO is
empty.
error. This bit is updated when the data register is read, and is cleared if the receive FIFO is
empty.
is received when the receive FIFO is full. This bit is cleared by reading the data register.
empty.
28
12
28
12
Reserved
Reserved
27
11
27
11
0x0000 0040
0x0000 0000
26
10
26
10
25
25
9
9
Doc ID 16252 Rev 8
24
24
8
8
Reserved
Reserved
23
23
7
7
SC_UA
SC_UA
RTAUT
RTTXI
DLE
22
22
rw
O
6
6
r
SC_UA
RTPAR
SC_UA
RTFLO
ERR
21
21
rw
W
5
5
r
STM32W108CB, STM32W108HB
RMER
ARTO
SC_U
ARTF
SC_U
DD
20
20
rw
R
4
4
r
SC_UA
SC_UA
RTPAR
RTRX
OVF
19
19
rw
3
3
r
SC_UA
SC_UA
RTTXF
RT2ST
REE
18
18
rw
P
2
2
r
SC_UA
RTRXV
SC_UA
RT8BI
17
AL
17
rw
1
1
T
r
SC_UA
RTCTS
SC_UA
RTRTS
16
16
rw
0
0
r
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