AT24C512C-XHD-B Atmel, AT24C512C-XHD-B Datasheet - Page 6

• Manufacturer Part Number: AT24C512C-XHD-B
• Manufacturer: Atmel

Specifications of AT24C512C-XHD-B

• Lead Free Status / Rohs Status: Compliant

4.
6
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (see
a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other
command (see
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The Atmel
b) after the receipt of the STOP bit and the completion of any internal operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be protocol reset
by following these steps: (a) Create a start condition, (b) clock nine cycles, (c) create another start condition followed by
a stop condition, as shown below. The device is ready for the next communication after the above steps have been
completed.
Figure 4-1.
Figure 4-2.
SCL
SDA
SDA OUT
Atmel AT24C512C
SDA IN
SCL
Start bit
Protocol Reset Condition
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Figure 4-5 on page
t
SU.STA
1
®
AT24C512C features a low-power standby mode which is enabled: a) upon power up and
t
7).
HD.STA
t
t
2
F
LOW
t
AA
Figure 4-4 on page
Dummy Clock Cycles
t
HIGH
3
t
HD.DAT
t
Figure 4-5 on page
LOW
7). Data changes during SCL high periods will indicate
8
t
t
SU.DAT
DH
9
7).
Start bit
t
R
8720A–SEEPR–9/10
t
SU.STO
Stop bit
t
BUF