853011BM IDT, Integrated Device Technology Inc, 853011BM Datasheet - Page 11

• Manufacturer Part Number: 853011BM
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 853011BM

• Number Of Outputs: 4
• Operating Supply Voltage (max): -3.8/3.8V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 0.415ns
• Operating Supply Voltage (min): -2.375/2.375V
• Mounting: Surface Mount
• Pin Count: 8
• Operating Supply Voltage (typ): -2.5/-3.3/3.3V
• Package Type: SOIC
• Duty Cycle: 52%
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

IDT™ / ICS™ LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ICS853011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
This section provides information on power dissipation and junction temperature for the ICS853011.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853011 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W
per Table 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
T
853011BM
ABLE
ABLE
Multi-Layer PCB, JEDEC Standard Test Boards
5A. T
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
5B. T
Power (core)
Power (outputs)
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power
The equation for Tj is as follows: Tj =
Tj = Junction Temperature
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
85°C + 0.157W * 103.3°C/W = 101.2°C. This is well below the limit of 125°C.
JA
A
= Ambient Temperature
= Junction-to-Ambient Thermal Resistance
HERMAL
HERMAL
Integrated
Circuit
Systems, Inc.
R
R
MAX
ESISTANCE
ESISTANCE
_MAX
MAX
= V
(3.8V, with all outputs switching) = 95mW + 61.88mW = 156.88mW
= 30.94mW/Loaded Output pair
CC_MAX
JA
JA
* I
FOR
FOR
EE_MAX
D
JA
8-
IFFERENTIAL
8-
JA
P
CC
PIN
= 3.8V * 25mA = 95mW
by Velocity (Linear Feet per Minute)
PIN
www.icst.com/products/hiperclocks.html
by Velocity (Meters per Second)
= 3.8V, which gives worst case results.
OWER
TSSOP, F
SOIC, F
JA
* Pd_total + T
ORCED
C
ORCED
-
TO
ONSIDERATIONS
C
-2.5V/3.3V LVPECL/ECL F
A
11
C
ONVECTION
11
101.7°C/W
ONVECTION
153.3°C/W
112.7°C/W
0
0
TM
devices is 125°C.
90.5°C/W
128.5°C/W
103.3°C/W
200
1
L
89.8°C/W
OW
115.5°C/W
JA
97.1°C/W
must be used.
500
2
ANOUT
S
REV. C NOVEMBER 2, 2005
KEW
, 1-
B
UFFER
TO
ICS853011
-2
TSD