SI3010-F-FSR Silicon Laboratories Inc, SI3010-F-FSR Datasheet - Page 82

• Manufacturer Part Number: SI3010-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3010-F-FSR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Si3018/19/10
Register 59. Spark Quenching Control
Reset settings = 0000_0000
82
Name
Bit
Type
7
6
5
4
3
2
1
0
Bit
Reserved Always write this bit to zero.
Reserved Always write this bit to zero.
Reserved Always write this bit to zero.
Name
GCE
SQ1
SQ0
RG1
TB3
R/W
TB3
D7
For South Korea PTT compliance, set this bit, in addition to the RZ bit, to synthesize a ringer
impedance to meet South Korea ringer impedance requirements. This bit should only be set
to meet South Korea PTT requirements and should only be set in conjunction with the RZ bit.
Spark Quenching.
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
Spark Quenching.
This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
Receive Gain 1 (Line-side Revision E or later).
This bit enables receive path gain adjustment.
0 = No gain applied to hybrid, full scale RX on line = 0 dBm.
1 = 1 dB of gain applied to hybrid, full scale RX on line = –1 dBm.
Guarded Clear Enable (Line-side Revision E or later).
This bit (in conjunction with the RZ bit set to 1), enables the Si3056 to meet BT’s Guarded
Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw
approximately 2.5 mA of current from the line while on-hook.
0 = default, DAA does not draw loop current.
1 = Guarded Clear enabled, DAA draws 2.5 mA while on-hook to meet Guarded Clear
requirement.
SQ1
R/W
0
0
1
0
0
1
D6
OHS2
OHS2
D5
0
1
X
0
1
X
SQ0
R/W
D4
SQ[1:0]
SQ[1:0]
00
00
11
00
00
11
D3
Rev. 1.05
RG1
R/W
D2
Function
Less than 0.5 ms
3 ms ±10% (meets ETSI standard)
26 ms ±10% (meets Australia spark quenching
spec)
Less than 0.5 ms
3 ms ±10% (meets ETSI standard)
26 ms ±10% (meets Australia spark quenching
spec)
Mean On-Hook Speed
Mean On-Hook Speed
GCE
R/W
D1
D0